Ziatech Corporation ZT 8809A, Руководство по эксплуатации

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Theory of Operation
STD BUS COMPATIBILITY
The ZT 8809A is fully compatible with Revision 2.3 of the STD-80
Series Bus Specification. This revision of the bus specification
includes definition of two new backplane interrupt request signals,
INTRQ1* and INTRQ2*, which replace the signals RESERVED and
CNTRL*, respectively. (An asterisk indicates an active low signal.)
Prior to ZT 8808 Revision 2.3, only one backplane interrupt request
INTRQ* existed, requiring frontplane cabling or sharing of the
interrupt if more than one backplane interrupt was in the system. STD
DOS uses INTRQ1* for the keyboard interrupt request from the
ZT 8844 Enhanced Graphics Adapter (EGA) card. See the discussion
of the interrupt system later in this chapter for details on these
interrupts.
The ZT 8809A also complies with the STD 32 Bus Specification,
class SA8 with no dynamic IOEXP support.
MEMORY AND I/O
Refer to Chapter 5, "Memory and I/O Capability," for a discussion of
the ZT 8809A’s memory allocation and I/O address space.
SERIAL COMMUNICATIONS
The ZT 8809A includes two asynchronous RS-232-C serial ports, one
of which is configurable for RS-422/485 use. Both serial ports are
implemented in one chip, the VL 16C452, which contains two
16C452 compatible serial ports. This section discusses system level
issues for serial communication. Refer to Chapter 8 for operation and
programming of these serial ports and to Appendix A for the proper
jumper configurations.
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