Ziatech Corporation ZT 8809A, Руководство по эксплуатации

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ZT 88CT08A/88CT09A CMOS Boards
Use of 80C88 Processor
The ZT 88CT09A uses an 80C88 microprocessor instead of the V20
used on non-CMOS versions. The 80C88 allows for a slower clock
speed, even a halted clock, for extremely low power operation.
Although the V20 is CMOS and also has a low power standby mode,
it does not allow for a clock speed slower than 2 MHz. The slowdown
and stopped clock modes are available on the ZT 88CT09A and are
described beginning on page 13-4.
Performance of the 80C88 processor is identical to that of the 8088
microprocessor. The 80C88 also contains bus hold circuitry that pulls
the data and address buses internal to the ZT 88CT09A to a valid
logic state if no driving source is present. A useful example of this is
during DMA accesses on the STD bus when the CPU is asked to
three-state its address and data buses to allow another bus master to
drive the bus.
Since the CPU is fully buffered from the STD bus, these buffers
actually three-state their outputs at DMA time, and their inputs
require a valid logic level. This logic level is required to avoid large
current consumption characteristic of CMOS parts when the inputs
are not at a valid high or low logic level. Instead of going to a three-
state level at DMA time, the CPU maintains the last logic level driven
unless another driving source is present. This provides the valid logic
level to the inputs of the STD bus buffers and thus conserves power.
If your system requires the use of the V20 processor, the 80C88 may
be replaced by the V20. However, this requires the addition of a
9 x 22 k
Ω
SIP pullup resistor on the data and address buses internal to
the ZT 88CT09A. Holes are provided on the printed circuit board for
this purpose at SIP location 8. Contact Ziatech for further information
regarding addition of these resistors.
13-3