Ziatech Corporation ZT 8809A, Руководство по эксплуатации

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Serial Communications (16C452)
Bit 4 This bit provides a loopback feature for diagnostic
testing of the 16C452. When bit 4 is set to logical 1, the
following occurs: the transmitter Serial Output (SOUT)
is set to the marking (logical 1) state, the receiver Serial
Input (SIN)
is disconnected, the output of the
Transmitter Shift register is "looped back" into the
Receiver Shift register input, the four Modem Control
inputs (CTS, DSR*, RLSD*, and RI*) are disconnected,
and the four Modem Control outputs (DTR*, RTS*,
OUT1, and OUT2) are internally connected to the four
Modem Control inputs. The Modem Control outputs
DTR* and RTS* are set to their inactive state (high).
In the diagnostic mode, data that is transmitted is
immediately received. This feature allows the processor
to verify the transmit-data and receive-data paths of the
16C452.
In the diagnostic mode, the receiver and
transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational, but the interrupts’
sources are now the lower four bits of the MCR instead
of the four Modem Control inputs. The interrupts are
still controlled by the Interrupt Enable register.
The 16C452 interrupt system can be tested by writing
into the lower six bits of the Line Status register and the
lower four bits of the Modem Status register. Setting any
of these bits to logical 1 generates the appropriate
interrupt (if enabled). The resetting of these interrupts is
the same as in normal 16C452 operation. To return to
normal operation, the register must be reprogrammed for
normal 16C452 operation and then bit 4 must be reset to
logical 0.
Bits 5 - 7 These bits are permanently set to logical 0.
8-32