Ziatech Corporation ZT 8809A, Руководство по эксплуатации

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Counter/Timers (8254)
Mode Definitions
The following modes are defined for use in describing the operation
of the 8254.
CLK Pulse: A rising edge, then a falling edge, in that order, of
a counter’s CLK input.
Trigger: A rising edge of a counter’s GATE input.
Counter Loading: The transfer of a count from the CR to the CE
(refer to Chapter 12, "Functional Description,"
page 12-7).
Timing diagrams for these modes are included in the Intel
Microprocessor and Peripheral Handbook, Volume II, 1988, pages
2-35 through 2-40.
Mode 0: Interrupt on Terminal Count
Mode 0 is typically used for event counting. After the Control Word
is written, OUT is initially low and remains low until the counter
reaches zero. OUT then goes high and remains high until a new count
or a new Mode 0 Control Word is written into the counter.
GATE = 1 enables counting
GATE = 0 disables counting
(GATE has no effect on OUT)
After the Control Word and initial count are written to a counter, the
initial count is loaded on the next CLK pulse. This CLK pulse does
not decrement the count, so for an initial count of N, OUT does not go
high until N + 1 CLK pulses after the initial count is written.
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