Ziatech Corporation ZT 8809A, Руководство по эксплуатации

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Serial Communications (16C452)
Table 8-3
16C452 Addressable Registers Summary.
0 DLAB = 0 0 DLAB = 0 1 DLAB = 0
2 3
Receive Buffer
(Read Only)
Transmit Buffer
(Write Only)
Interrupt Enable
Register
Interrupt Iden-
tify Register
(Read Only)
Line Control
Register
Register Address
Bit
No.
Data Bit 0*
Data Bit 0
Enable Receive
Buffer Full
Interrupt (MSI)
"0" if
Interrupt
Pending
Word Length
Select Bit 0
(WLS0)
RBR THR
IER IIR LCR
0
Data Bit 1
Data Bit 1
1
Enable Transmit
Buffer Empty
Interrupt (RSI)
Interupt ID
Bit (0)
Word Length
Select Bit 1
(WLS1)
2 Data Bit 2 Data Bit 2
Enable Receive
Status Interrupt
(TBI)
Interrupt ID
Bit (1)
Number
of Stop
Bits (STB)
3 Data Bit 3 Data Bit 3
Enable Modem
Status Interrupt
(RBI)
0
Parity Enable
(PEN)
4
Data Bit 4 Data Bit 4
0 0
Even Parity
Select (EPS)
5
Data Bit 5 Data Bit 5
0 0
Stick Parity
6
Data Bit 6 Data Bit 6
0
0 Set Break
7
Data Bit 7 Data Bit 7
0 0
Divisor Latch
Access Bit
(DLAB)
*Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
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