Ziatech Corporation ZT 8809A, Руководство по эксплуатации

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CPU Description
V20 ARCHITECTURAL ENHANCEMENTS
This section focuses on the architectural enhancements that the V20
provides which improve its speed over that of the 8088 micro-
processor. These improvements include:
•
Dual data bus in EXU
•
Effective address generator
•
16/32-bit temporary registers/shifters (TA, TB)
•
16-bit loop counter (LC)
•
Program Counter (PC) and Prefetch Pointer (PFP)
Dual Data Bus
A dual data bus has been adopted for the V20 EXU in order to reduce
the number of processing steps for instruction execution. The two
data buses are both 16 bits wide, improving the addition/subtraction
and logical and comparison operations by approximately 30 percent
over single-bus architectures.
Effective Address Generator
A circuit has been included for direct hardware calculation of
effective addresses for accessing memory. Calculating an effective
address by the microprogramming method normally requires 5 to 12
clock cycles. This circuit requires only two clock cycles for addresses
to be generated for any addressing mode, thus improving processing
speed several times.
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