Ziatech Corporation ZT 8809A, Руководство по эксплуатации

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Theory of Operation
DMA Operation
Figure 3-5 shows the interface between the ZT 8809A and an STD
bus DMA controller. The signals shown are required for proper
operation of devices on the STD bus during DMA cycles.
The DMA cycle is initiated when the controller asserts the bus request
signal BUSRQ* on the STD bus. The ZT 8809A responds to this
request by waiting for the CPU to finish the current instruction, then
acknowledges the release of the bus by asserting the bus acknowledge
signal BUSAK*. Simultaneously, the ZT 8809A turns the address
buffers inward to allow access to on-board memory by the DMA
controller. The controller is then free to transfer data between an STD
bus board and the ZT 8809A or between two STD bus boards.
The STD bus DMA controller must meet timings for read and write
cycles as defined by the STD-80 Series Bus Specification. Refer to
the timings in Appendix B for the ZT 8809A read and write cycles, as
well as timings for the transfer of bus control during DMA cycles.
For further details on transfer of STD bus control for DMA, refer to
Chapter 5, "Memory and I/O Capability."
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