Ziatech Corporation ZT 8809A, Руководство по эксплуатации

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Theory of Operation
Clock Slowdown
Power consumption for CMOS logic is directly proportional to the
switching speed of the device. The higher the clock frequency, the
greater the power dissipation.
In order to minimize the power
consumption on the ZT 88CT09A boards, the Clock Slowdown
feature has been included to allow dynamic switching of the processor
clock speed between the normal frequency and that frequency divided
by 256.
The ZT 88CT08A may be selected to run at either 5 MHz or
19.5 kHz, and the ZT 88CT09A at either 8 MHz or 31.25 kHz.
Selection is done at printer port bit 3 of the Control Port register at
I/O address 037Ah. Writing to this bit controls the Select In (SLIN*)
signal, which then controls the clock speed; a logical 0 selects the
slowed clock frequency and a logical 1 selects the normal frequency,
provided jumper W46B is installed.
Note: SLIN* is also used to map in the lower half of a 256K
EPROM. If W67 is installed and W68 is in the "A" position (for
512K SRAM devices), writing a logical 1 to bit 3 of the Control Port
register will also enable read cycles to the lower half of the EPROM
in socket 5D1.
SLIN* is one of four shared printer port signals described in further
detail in Chapter 9, "Centronics Printer Interface."
Slowing down the processor clock is useful for power-critical
applications where full-speed processing is not always a requirement.
For example, a situation may exist in which processing occurs only
during certain time intervals. The software is able to slow down the
clock for non-critical processing times, and yet continue to process in
order to monitor non-critical events such as checking time of day.
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