Ziatech Corporation ZT 8809A, Руководство по эксплуатации

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Memory and I/O Capability
INPUT/OUTPUT ADDRESSING
The I/O addressability of the ZT 8809A is 64 Kbytes, equal to that of
the V20 and 8088 series microprocessors. All 16 STD bus address
lines are driven during I/O read or write cycles. The upper eight
address lines remain at zero during 8-bit I/O instructions. All devices
on-board are accessed with 16 bits of address. During on-board
accesses, all address lines along with I/O Request (IORQ*) are driven
to the backplane. For details on the timing of I/O bus cycles, refer to
the timing diagrams in Appendix B.
The I/O devices on board include the two serial ports, the Centronics
compatible printer port, the three 16-bit counter/timers, and the
programmable interrupt controller. The real-time clock is a memory
mapped device sharing a memory address with the 32 Kbyte static
RAM on board. Refer to the description of the real-time clock in
Chapter 10 for further details on this shared memory address.
Figure 5-8 represents an I/O map for both STD DOS and non-DOS
systems.
The I/O addresses do not vary like the memory
configurations. In the figure, all shaded areas represent free I/O space
for off-board use. If using STD DOS, refer to the STD DOS system
manual for recommendations as to where new I/O boards may be
added in the I/O address space to avoid conflict with other DOS
devices in the system.
Special consideration must be made when placing I/O boards that
decode less than the full 16 bits of I/O address into the ZT 8809A
STD system. For example, if an I/O board decodes only 8 bits, then
all of the upper 8 bits of the I/O address are "don’t cares" to this
board. It is important not to map this board into the same address
space occupied by the lower 8 bits of any device on-board or in the
system backplane.
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