Ziatech Corporation ZT 8809A, Руководство по эксплуатации

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CPU Description
DMA SUPPORT
The STD-80 Series Bus Specification defines two signals used by
processor boards and DMA devices to exchange control of the STD
bus for DMA transfers.
These two signals are Bus Request
(BUSRQ*) and Bus Acknowledge (BUSAK*), pins 42 and 41 on the
STD bus, respectively. Use of DMA increases data transfer speeds
from one device to another, frees the processor for other tasks while
the transfer takes place, and may significantly increase system
throughput.
The ZT 8809A supports DMA accesses via the BUSRQ* and
BUSAK* STD bus signals under the supervision of an external
device’s DMA controller.
When the DMA controller asserts
BUSRQ*, the ZT 8809A bus arbiter pulses the Request/Acknowledge
(RQ/AK) [RQ/GT] signal to the V20, indicating that the V20 should
relinquish the processor bus. After completing its current instruction,
the V20 pulses RQ/AK back to the ZT 8809A bus arbiter, which
asserts BUSAK* to the STD bus.
At the same time, the ZT 8809A turns its address and data buffers to
point inward to allow the DMA device to access the ZT 8809A
memory and tri-states its control signals at the STD bus. The DMA
device is then free to transfer data independent of the V20 between
STD bus boards or between an STD bus board and the ZT 8809A
memory. All ZT 8809A memory is accessible to DMA devices except
the 32 Kbyte static RAM. The DMA controller must meet the 5 and
8 MHz timings of the STD-80 Series Bus Specification. Refer to
Appendix B for details on the bus control exchange timing during the
start and end of a DMA transfer cycle.
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