Ziatech Corporation ZT 8809A, Руководство по эксплуатации

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CPU Description
WAIT-STATE GENERATOR
The ZT 8809A contains a one wait-state generator for use with slower
memory and I/O boards, to allow for an increase in the memory and
I/O access time. The V20 processor extends the four-clock memory
and I/O cycles to five clocks when one wait state is requested at its
READY input. Proper selection of jumper W36 chooses between zero
(W36A) and one (W36B) wait state.
More wait states may be inserted by the particular board needing extra
time by assertion of the WAITRQ* STD bus signal, which in turn
causes the READY line to be driven low (inactive). Use of the
external board’s wait request, which should occur only when that
board is selected, yields optimum system performance. In this way,
only a subset of I/O or memory cycles is extended rather than all of
them, as is the case when an on-board wait state is selected. Refer to
the timing diagrams in Appendix B for details on the wait request
timing.
Table 6-3 shows the memory speed requirements for the ZT 8808A
and ZT 8809A at 5 and 8 MHz speeds with zero and one wait state.
Table 6-3
Memory Access Times.
Memory Access Times
Wait State (Time for Address to Data)
ZT 8808A ZT 8809A
Zero Wait States 380 ns 210 ns
One Wait State 580 ns 335 ns
6-21