SRS Labs QMS 100 Series, Руководство пользователя

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Description of Schematics B-13
Technical Reference
with the correct amplitude and phase into the primary drive inductor, T401, to cancel the charge
injected via the FET gates.
DC Potentials
In addition to the RF, DC potentials of about
±
1/12th the RF peak-to-peak value is required for the
two rod pairs. The op-amp U403A is the error amplifier which maintains the negative potential equal to
a fraction of the set RF level. When DC_SET goes up, the output of the op-amp goes up, increasing the
current in Q406, increasing the current in Q407, bringing down the collector of Q407, which is the
output of the negative potential voltage regulator.
The op-amp U403B is the error amplifier for the positive potential. The positive potential is compared
to the negative potential by R431 and R432. When the negative potential increases, the non-inverting
input to U403B will go down, lowering the op-amp output, increasing the current in Q405, increasing
the current in Q404, thereby increasing the positive potential until it matches the magnitude of the
negative potential.
Schematic name: QMSE_B2
Filament Heater Supply
The sensitivity of the quadrupole depends on the filament emission current, which depends on the
filament temperature and bias with respect to the grid. As the grid to filament bias is fixed to optimize the
electron impact ionization crossection, the filament emission current is controlled by controlling the
filament temperature via the filament heater current’s duty cycle.
A switching power supply, which is synchronized to a sub-multiple of the master clock at 172.8kHz, is
used to provide heater power to the filament. (Note that two clocks are required for each cycle, so the
primary drive current is at 86.4kHz.) The switcher’s transformer has a 6:1 turns ratio, reducing the
+24V input to a 4V output, which leaves about 3.5V after rectification in the dual Schottky diode,
D501.
The primary of the transformer is operated from the +24VDC supply, and is driven differentially by a
pair of IRF530 MOSFETs. An LT3525 switching controller, U501, is used to drive the FET gates. The
duty cycle of the gate drive depends on the voltage at the COMP pin (pin 9). A voltage of about 0.9V
or below will set the duty cycle to zero. The duty cycle increases to a maximum near 50% (for each
gate) as the voltage on this input is increased to about 3.3V.
The analog switch, U500, controls the source of the signal to the COMP pin. If EMIT_CTL is low (as
it is after a reset) then the DAC signal EMIT_SET is connected directly to the COMP pin allowing for
direct control of the filament heater’s duty cycle by the CPU. This mode is used when the filament is first
turned “on” to verify that the pressure is low enough to allow the filament to remain “on”.
When EMIT_CTL is set high, the COMP pin is connected to the compensation capacitor C500, which
will be charged and discharged by the transconductance error amplifier in U501. The error amplifier will
compare the EMIT_SET voltage (or the attenuated EMIT_SET voltage, depending on the state of the