Samsung S5PC110, Руководство пользователя

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S5PC110_UM 3 SERIAL PERIPHERAL INTERFACE
3-3
3.2.1.5 Chip Select Control
Chip select XspiCS# is active low signal. In other words, a chip is selected when XspiCS# input is 0.
XspiCS# can be controlled automatically or manually.
When you use manual control mode, AUTO_N_MANUAL must be cleared (Default value is 0). XspiCS# level is
controlled by NSSOUT bit.
When you use auto control mode, AUTO_N_MANUAL must be set as 1. XspiCS toggled between packet and
packet automatically. Inactive period of XspiCS is controlled by NCS_TIME_COUNT. NSSOUT is not available at
this time.
3.2.1.6 High Speed Operation as Slave
S5PC110 SPI supports Tx/Rx operations upto 50MHz, but there is a limitation. When S5PC110 SPI works as a
slave, it consumes large delay over than 15ns in worst operating condition. Such a large delay can cause setup
violation at SPI master device. To overcome the problem, S5PC110 SPI provides fast slave Tx mode by setting 1
to HIGH_SPEED bit of CH_CFG register. In that mode, MISO output delay is reduced by half cycle, so that the
SPI master device has more setup margin.
However, the fast slave Tx mode can be used only when CPHA = 0.
3.2.1.7 FeedBack Clock Selection
Under SPI protocol spec, SPI master should capture the input data launched by slave (MISO) with its internal
SPICLK. If SPI runs at high operating frequency such as 50MHz, it is difficult to capture the MISO input because
the required arrival time of MISO, which is an half cycle period in S5PC110, is shorter than the arrival time of
MISO that consists of SPICLK output delay of SPI master, MISO output delay of SPI slave, and MISO input delay
of SPI master. To overcome the problem, S5PC110 SPI provides 3 feedback clocks that are phase-delayed clock
of internal SPICLK.
A selection of feedback clock depends on MISO output delay of SPI slave. To capture MISO data correctly, it is
selected the feedback clock that satisfies the following constraint.
t
SPIMIS
(s) < t
period
/2 - t
SPISOD
* t
SPIMIS
(s): MISO input setup time of SPI master on a given feedback clock selection 's'
* t
SPISOD
: MISO output delay of SPI slave
* t
period
: SPICLK cycle period
If multiple feedback clocks meet the constraint, the feedback clock with smallest phase delay should be selected.
It is because a feedback clock with large phase delay may capture data of next cycle.
For example of S5PC110 SPI CH1 with master configuration of 50MHz operating frequency, 1.8V external voltage
and 15pF load, 270 degree phase-delayed feedback clock should be used if the MISO output delay of SPI slave is
assumed as 11ns (t
SPIMIS
(s) < 10ns - 11ns = -1ns).
If the operating clock frequency is 33MHz and other conditions are the same as the previous example, it is better
to use 180 degree phase-delayed feedback clock (t
SPIMIS
(s) < 15ns - 11ns = 4ns).