Samsung S5PC110, Руководство пользователя

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S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT
5-5
The IEC also includes a Design for Test (DFT) interface. This enables easier control over the scaling hardware
during production testing of the SoC device.
The IEC is an AMBA compliant, SoC peripheral that is developed, tested, and licensed by ARM Limited. The IEC
features are as follows:
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AMBA APB compliant.
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Defined interfaces between the IEC and CMU/APC1 via PMU that is necessary for a complete energy
management solution.
•
An abstract interface to the underlying system-specific clock multiplexing and dynamic voltage or power
control. This is through mapping to an implementation-defined set of index levels:
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That correspond with the CMU frequencies that can be selected, and
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That enables the voltage steps for the corresponding dynamic or adaptive power supply technology and
consequently supports multiple operating performance points.
•
An encoded interface protocol that provides a performance index to S5PC110x’s CMU and APC1 blocks.
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Dynamic Voltage Scaling (DVS) emulation support enables a run fast then idle mode of operation.
•
An API interface for efficient control and monitoring:
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Implementation-independent fractional performance setting interface to support performance prediction
algorithms without hard-coded frequencies.
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Implementation-independent interrogation of performance-level quantization mapping levels to enable
performance prediction software to adapt to the processor clock frequencies provided.
−
SoC-specific configuration interrogation, consisting of processor and IEC clock frequencies in kHz, and
performance level mapping provided by the S5PC110x’s CMU.
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Supports maximum performance signaling for real time subsystems that enables:
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The maximum performance level to be requested regardless of the current programmed target
performance level.
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You to decide the events that activate this mode.
•
Monitoring for IEM-specific algorithms, through a multi-channel interface designed to support automatic
accumulation of system metrics.
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Supports synchronization handshaking with synchronous and asynchronous bridges to control entry and exit
from maximum performance mode.
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Test registers for use in block and system level integration testing.
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System level integration testing using externally applied integration vectors.
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Debug mode to test clock generation with maximum voltage.
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ID support registers to port software driver compliance.