Samsung S5PC110, Руководство пользователя

Страница: 623 / 2426

S5PC110_UM 3 ONENAND CONTROLLER
3-21
3.7 I/O INTERFACE
Signal I/O Description PAD Type
ADDR[15:0] I/O
Address Bus outputs, during memory read/ write
address phase Xm0ADDR
[15:0]
muxed
DQ[15:0] I/O
Data Bus outputs address during memory read/ write
address phase, inputs data during memory read data
phase and outputs data during memory write data
phase.
Xm0DATA
[15:0]
muxed
nCE[1:0] O
Chip Selects are activated when the address of a
memory is within the address region of each bank.
Xm0CSn[3:2] can be assigned to either SROMC or
OneNAND controller by System Controller SFR setting.
Active LOW.
Xm0CSn
[5:4]
muxed
nWE O
Write Enable indicates that the current bus cycle is a
write cycle. Active LOW.
Xm0WEn muxed
nOE O
Output Enable indicates that the current bus cycle is a
read cycle. Active LOW.
Xm0OEn muxed
INT[1:0] I
Interrupt inputs from OneNAND memory Bank 0, 1.
If OneNAND memory is not used, these signals should
be tied to zero.
Xm0FRnB
[5:4]
muxed
nAVD O
Address valid output. In the POP products, address and
data are multiplexed. Xm0ADDRVALID indicate when
the bus is used for address. Active LOW.
Xm0FCLE muxed
nRP O
System reset output for OneNAND memory.
Active LOW. Xm0FWEn muxed
CLK O
Static memory clock for synchronous static memory
devices.
Xm0FALE muxed
NOTE:
The INT pin of each OneNAND Device must be pulled up by a 4.7K-ohm external pull-up resistor.