Samsung S5PC110, Руководство пользователя

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S5PC110_UM 7 SD/MMC CONTROLLER
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7.9.2 SDMA SYSTEM ADDRESS REGISTER
7.9.2.1 SDMA System Address Register
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SDMASYSAD0, R/W, Address = 0xEB00_0000
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SDMASYSAD1, R/W, Address = 0xEB10_0000
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SDMASYSAD2, R/W, Address = 0xEB20_0000
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SDMASYSAD3, R/W, Address = 0xEB30_0000
This register contains the physical system memory address used for DMA transfers.
SDMASYSAD Bit Description Initial State
SDMASYSAD [31:0] SDMA System Address
This register contains the system memory address for a DMA
transfer. If the Host Controller stops a DMA transfer, this register
points to the system address of the next contiguous data
position. It is accessed if no transaction is in-progress (i.e., after
a transaction has stopped). Read operations during transfers can
return an invalid value.
The Host Driver initializes this register before starting a DMA
transaction. After DMA has stopped, the next system address of
the next contiguous data position is read from this register.
The DMA transfer waits at the every boundary specified by the
Host SDMA Buffer Boundary in the Block Size register. The Host
Controller generates DMA Interrupt to request the Host Driver to
update this register. The Host Driver set the next system address
of the next data position to this register. If the most upper byte of
this register (003h) is written, the Host Controller restarts the
DMA transfer. If restarting DMA by the Resume command or by
setting Continue Request in the Block Gap Control register, the
Host Controller starts at the next contiguous address stored here
in the System Address register.
0x00