Samsung S5PC110, Руководство пользователя

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S5PC110_UM 5 USB2.0 HS OTG
5-51
GLPMCFG Bit Description R/W Initial State
EnblSlpM [7] For UTMI+ interface: The application uses this bit to control
utmi_sleep_n assertion to the PHY in the L1 state. For the
host, this bit is valid only in Local Device mode.
• 1’b0: utmi_sleep_n assertion from the core is not
transferred to the external PHY.
•
1’b1: utmi_sleep_n assertion from the core is transferred
to the external PHY when utmi_l1_suspend_n cannot be
asserted.
R/W 1'b0
Host Mode: The remote wakeup value to be sent in the LPM
transaction’s wIndex field. R/W 1'b0 bRemoteWake [6]
Device Mode: This field is updated with the received
bRemoteWake LPM token’s bmAttribute when an
ACK/NYET/STALL response is sent to an LPM transaction. R 1'b0
HIRD [5:2] Host Mode: The value of HIRD to be sent in an LPM
transaction. This value is also used to initiate resume for a
duration TL1HubDrvResume1 for host initiated resume R/W 4'b0
AppL1Res [1] Handshake response to LPM token pre-programmed by
device application software. The response depends on
GLPMCFG.LPMCap. If GLPMCFG.LPMCap is 1’b0, the
core always responds with a NYET. If GLPMCFG.LPMCap
is 1’b1, the core responds as follows:
•
1: ACK Even though an ACK is pre-programmed, the core
responds with an ACK only on a successful LPM
transaction. The LPM transaction is successful if: - There
are no PID/CRC5 errors in both the EXT token and the LPM
token (else ERROR) - A valid bLinkState = 0001B (L1) is
received in the LPM transaction (else STALL) - No data is
pending in the Transmit queue (else NYET)
• 0: NYET The pre-programmed software bit is overridden
for response to LPM token when: - The received bLinkState
is not L1 (STALL response) - An error is detected in either of
the LPM token packets due to corruption (ERROR
response).
R 1'b0
LPMCap [0] LPM-Capable (LPMCap) The application uses this bit to
control the DWC_otg core LPM capabilities. If the core
operates as a non-LPM-capable host, it cannot request the
connected device/hub to activate LPM mode. If the core
operates as a non-LPM-capable device, it cannot respond to
any LPM transactions.
•
1’b0: LPM capability is not enabled.
•
1’b1: LPM capability is enabled. Otherwise, reads return
0.
R/W 1'b0