Samsung S5PC110, Руководство пользователя

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S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT
5-36
5.5.3.6 Minimum Limit Register (APC_MINVDD_LIMIT, R/W, Address = 0xE070_0018)
APC_MINVDD_LIMIT Bit Description Initial State
Reserved [7] Read undefined. Write as zero. 0
Minimum core voltage [6:0] Minimum SoC operating core voltage. 0x00
5.5.3.7 VDD Check Register (APC_VDDCHK, R/W, Address = 0xE070_001C)
APC_VDDCHK Bit Description Initial State
vddchkd[3:0] [7:4] The upper nibble of this register holds the four LSBs of
the 12-bit vddchkd counter. 0x0
vddchk[3:0] [3:0] Evaluation time period during the integration of the slack
in the closed 0x0
5.5.3.8 VDD Delay Time Register (APC_VDDCHKD, R/W, Address = 0xE070_0020)
APC_VDDCHKD Bit Description Initial State
vddchkd[11:4] [7:0] Holds the upper eight bits of the 12-bit vddchkd counter. 0x00
5.5.3.9 VDD Pre-delay Select Register (APC_PREDYSEL, R/W, Address = 0xE070_0024)
APC_PREDYSEL Bit Description Initial State
Reserved [7:3] Read undefined. Write as zero. 0
Pre-delay [2:0] Selects the predelay value for the HPM. 0x7
5.5.3.10 APC Interrupt Mask Register (APC_IMASK, R/W, Address = 0xE070_0028)
APC_IMASK Bit Description Initial State
Reserved [7] Read undefined. Write as zero. 0
APB Write Discard [6] The APB write is discarded. 0
PWI Transaction Done [5] The PWI transaction is completed. 0
Error Detected in PWI [4] Error is detected in the PWI response frame. 0
No PWI Slave Response [3] No response frame detected on the PWI interface. 0
Output Voltage Clamped [2] The output voltage is clamped to the minimum voltage
limit or to the zero voltage. 0
Low VDD Timeout [1] Vdd has not reached the optimum voltage in the closed-
loop mode for the voltage upward slew within the
hardware defined time period. 0
Undershoot Interrupt [0] Undershoot interrupt. 0