Samsung S5PC110, Руководство пользователя

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S5PC110_UM 5 INTELLIGENT ENERGY MANAGEMENT
5-4
5.2 FUNCTIONAL DESCRIPTION OF INTELLIGENT ENERGY MANAGEMENT
To support IEM, S5PC110 includes special IPs, namely:
•
Intelligent Energy Controller
•
Power Management Unit supporting IEM
•
Clock Management Unit (CMU) supporting Dynamic Clock Generation
−
Clock Management Unit in System Controller acts as Dynamic Clock Generator
•
Advanced Power Controller (APC1) supporting Dynamic Voltage Control
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APC1 acts as Dynamic Voltage Controller
•
Power Supply Unit supporting Dynamic Voltage Scaling
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Power Supply Unit is the only off-chip component.
•
Hardware Performance Monitor (HPM)
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This is optional and required only for a closed loop system
Figure 5-2
shows the on-chip IEM components required for a complete solution of IEM and how each component
are connected.
5.2.1 IEM SYSTEM COMPONENTS
5.2.1.1 Intelligent Energy Controller
The Intelligent Energy Controller (IEC) from ARM is designed to reuse in a wide variety of AMBA based designs
and has a standard APB slave interface to program the registers. The IEC provides an Applications Programming
Interface (API) for the IEM software. The IEC connects via defined interfaces to SoC-specific components such as
the APC1.
The IEC uses prediction performance level requests from the IEM software. The performance setting is
communicated to the IEC in order to control the System-on-Chip specific and product platform scaling hardware
and to achieve desired system performance. Battery life is extended by lowering the operating frequency and
voltage of SoC components, such as the processor, and consequently reducing energy consumption.
The IEC provides an abstracted view of the SoC-specific performance scaling hardware. It is responsible for
translating the performance prediction made by the IEM software (0-100% of maximum performance) to an
appropriate performance point at which the system runs and then controlling the scaling hardware to achieve
operation at that target point. To achieve this, IEC sends a target performance request to the CMU and APC1.
The IEC also measures the work done in the system to ensure that the software deadlines are not missed.
Additionally, the IEC supports a maximum performance hardware request feature. The IEC is designed to map to
an implementation-defined set of index levels. You must configure the IEC to define the CMU frequencies and
APC1 voltage levels that can be selected. These frequencies and voltages depend on the capabilities of the
dynamic or adaptive power supply technology to support multiple operating performance points.
The IEC interfaces to the CMU and APC1 blocks via PMU through a thermometer encoded interface protocol,
which indicates to the IEC the current performance level. This protocol is specified to support interfacing across
asynchronous clock domains between high-speed PLL and clock-generator and low-speed voltage scaling
hardware. The IEC provides an encoded performance index to S5PC110’s CMU and APC1 blocks.