Samsung S5PC110, Руководство пользователя

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S5PC110_UM 7 SD/MMC CONTROLLER
7-48
PRNSTS Bit Description Initial State
require to wait for it to stabilize. Changing from 0 to 1 generates a
Card Insertion interrupt in the Normal Interrupt Status register and
changing from 1 to 0 generates a Card Removal interrupt in the
Normal Interrupt Status register. The Software Reset For All in the
Software Reset register does not affect this bit. If a card is removed
while its power is on and its clock is oscillating, the Host Controller
clears SD Bus Power in the Power Control register and SD Clock
Enable in the Clock Control register.
If this bit is changed from 1 to 0, the Host Controller immediately
stops driving CMD and DAT[3:0] (tri-state). In addition, the Host
Driver must clear the Host Controller by the Software Reset For All
in Software Reset register. The card detect is active regardless of
the SD Bus Power.
1 = Card Inserted
0 = Reset or Debouncing or No Card
Reserved [15:12] Reserved
BUFRDRDY [11] Buffer Read Enable (ROC)
This status is used for non-DMA read transfers. The Host Controller
implements multiple buffers to transfer data efficiently. This read
only flag indicates that valid data exists in the host side buffer status.
If this bit is 1, readable data exists in the buffer. A change of this bit
from 1 to 0 occurs if all the block data is read from the buffer. A
change of this bit from 0 to 1 occurs if block data is ready in the
buffer and generates the Buffer Read Ready interrupt.
1 = Enables Read
0 = Disables Read 0
BUFWTRDY [10] Buffer Write Enable (ROC)
This status is used for non-DMA write transfers. The Host Controller
implements multiple buffers to transfer data efficiently. This read
only flag indicates if space is available for write data. If this bit is 1,
data is written to the buffer. A change of this bit from 1 to 0 occurs if
all the block data is written to the buffer. A change of this bit from 0
to 1 occurs if top of block data is written to the buffer and generates
the Buffer Write Ready interrupt.
1 = Write enable
0 = Write disable 0
RDTRANACT [9] Read Transfer Active (ROC)
This status is used to detect completion of a read transfer.
This bit is set to 1 for either of the following conditions:
(1) After the end bit of the read command.
(2) If writing a 1 to Continue Request in the Block Gap Control
register to restart a read transfer.
This bit is cleared to 0 for either of the following conditions:
(1) If the last data block as specified by block length is transferred to
the System.
(2) If all valid data blocks have been transferred to the System and
no current block transfers are being sent as a result of the Stop At
Block Gap Request being set to 1. A Transfer Complete interrupt is
0