Samsung S5PC110, Руководство пользователя

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S5PC110_UM 4 POWER MANAGEMENT
4-29
4.7.4.1 Status of PLL after Wake-Up Event
When the S5PC110 wakes up from STOP mode or SLEEP mode by an External Interrupt, a RTC alarm wakeup
and other wakeup events, the PLL is turned “ON” automatically. However, the clock supply scheme is quite
different. The initial-state of the S5PC110 after wake-up from the SLEEP mode is almost the same as the Power-
On-Reset state except that the contents of the external DRAM is preserved. On the other hand, the S5PC110
automatically recovers the previous working state after wake-up from the STOP mode. The following
Table 4-8
shows the states of PLLs and internal clocks after wake-ups from the power-saving modes.
Table 4-8 The Status of MPLL and SYSCLK After Wake-Up
Mode before
wake-up
MPLL on/off after
wake up
SYSCLK after wake up and
before the lock time
SYSCLK after the lock time
by internal logic
IDLE unchanged PLL Output PLL Output
DEEP-IDLE off
→
on PLL Output PLL Output
STOP off
→
on PLL reference clock PLL Output
DEEP-STOP off
→
on PLL reference clock PLL Output
SLEEP off
→
off PLL reference clock PLL reference clock
4.7.5 DAC
DAC has two power modes, namely, Run and Power-down mode
•
In Run mode, DAC sends and receives data normally. (Iop = min. 19mA, typ. 23mA, max. 27mA)
•
In Power-down mode, all power to DAC is off internally. (Ipd = max. 100uA)
In NORMAL mode, both power modes can be used. If DAC is in use, then it is in Run mode. Otherwise, it can
enter into Power-down mode to save static power by setting register in TVOUT logic.
In IDLE mode, and DEEP-IDLE mode where TOP block is on, DAC keeps its operation or power state in
NORMAL.
Before entry to DEEP-IDLE mode where TOP block is ”OFF”, STOP and SLEEP mode, it is recommended that
DAC enter into Power-down mode.