Samsung S5PC110, Руководство пользователя

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S5PC110_UM 5 USB2.0 HS OTG
5-49
5.8.3.14 Core LPM Configuration Register (GLPMCFG, R/W, Address = 0xEC00_0054)
This register controls the operation of the core’s LPM and HSIC capabilities. It also contains status bits pertaining
to these features.
GLPMCFG Bit Description R/W Initial State
Reserved [31:28] - - 4'b0
LPM_RetryCnt_
Sts [27:25] Number of LPM host retries remaining to be transmitted for
the current LPM sequence.
R 3'b0
SndLPM [24] When the application software sets this bit, an LPM
transaction containing two tokens, EXT and LPM, is sent.
The hardware clears this bit once a valid response (STALL,
NYET, or ACK) is received from the device or the core has
finished transmitting the programmed number of LPM
retries. Note: This bit must only be set when the host is
connected to a local port. R_W
S_SC
1'b0
LPM_Retry_Cnt [23:21] When the device gives an ERROR response, this is the
number of additional LPM retries that the host performs until
a valid device response (STALL, NYET, or ACK) is received.
R/W 3'b0
LPM_Chnl_Indx [20:17] The channel number on which the LPM transaction must be
applied while sending an LPM transaction to the local
device. Based on the LPM channel index, the core
automatically inserts the device address and endpoint
number programmed in the corresponding channel into the
LPM transaction.
R/W 4'b0
L1ResumeOK [16] Indicates that the application or host can start a resume
from the Sleep state. This bit is valid in the LPM Sleep (L1)
state. It is set in Sleep mode after a delay of 50
μ
s
(TL1Residency). The bit is reset when SlpSts is 0
• 1’b1: The application/core can start resume from the
Sleep state
•
1’b0: The application/core cannot start resume from the
Sleep state
R 1'b0
Host Mode: The host transitions to the Sleep (L1) state as a
side-effect of a successful LPM transaction by the core to
the local port with an ACK response from the device. The
read value of this bit reflects the port’s current sleep status.
The core clears this bit after:
•
The core detects a remote L1 Wakeup signal;
•
The application sets the Port Reset bit or the Port
L1Resume bit in the HPRT register; or
•
The application sets the L1Resume/ Remote Wakeup
Detected Interrupt bit or Disconnect Detected Interrupt bit in
the Core Interrupt register (GINTSTS.L1WkUpInt or
GINTSTS.DisconnInt, respectively).
SlpSts [15]
Device Mode: This bit is set as long as a Sleep condition is
present on the USB bus. The core enters the Sleep state
when an ACK response is sent to an LPM transaction and
R 1'b0