Samsung S5PC110, Руководство пользователя

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S5PC110_UM 5 USB2.0 HS OTG
5-32
5.8.3.2 OTG Interrupt Register (GOTGINT, R/W, Address = 0xEC00_0004)
The application reads this register at the time of OTG interrupt. To clear the OTG interrupt, application clears the
bits in this register.
GOTGINT Bit Description R/W Initial State
Reserved [31:20] - - 12'h0
DbnceDone
[19] Debounce Done
The core sets this bit if the debounce is complete after the
device connects. This bit is valid if the HNP Capable or SRP
Capable bit is set in the Core USB Configuration register.
R_SS_
WC
1'b0
ADev
TOUTChg [18] A-Device Timeout Change
The core sets this bit to indicate that the A-device has timed
out while waiting for the B-device to connect. R_SS_
WC
1'b0
HstNegDet [17] Host Negotiation Detected.
The core sets this bit if it detects a host negotiation request
on the USB. R_SS_
WC
1'b0
Reserved [16:10] - - 7'h0
HstnegSuc
StsChng [9] Host Negotiation Success Status Change
The core sets this bit on the success or failure of a
USB host negotiation request. R_SS_
WC
1'b0
SesReq
SucStsChng [8] Session Request Success Status Change
The core sets this bit on the success or failure of a session
request. R_SS_
WC
1'b0
Reserved [7:3] - - 5'h0
SesEndDet [2] Session End Detected
The core sets this bit if the b_valid signal is deasserted.
R_SS_
WC
1'b0
Reserved [1:0] - - 2'h0