Samsung S5PC110, Руководство пользователя

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S5PC110_UM 2 ADVANCED CRYPTO ENGINE
HASH_MSG_SIZE_LOW & HASH_MSG_SIZE_HIGH
As shown in the above diagram, the two registers form a 64-bit counter. When you write values into them, they are
initialized with HWDATA. As data words are written through AHB or FIFO, the counter decreases by itself. When
the counter is about to become zero, the internal logic generates correct “i_last_word” and “i_last_byte_sel”
signals for the IP.
Note that the unit of this counter is byte. The maximum counting range is (264 – 1) bytes, which is large than
specified in the SHA1 specification.
In certain cases, you can use HASH_MSG_SIZE_HIGH and HASH_MSG_SIZE_LOW. A typical example would
be multi-part hashing (partial result is involved) without knowing the total message size in advance. In this case,
you can initialize the counter with a “big” number (such as 64’h80000000_00000000) for all the parts except the
last one. While processing the last part, through which the message will be known, you should initialize this
counter with the real message size.
HASH_IV_1 ~ HASH_IV_5
The values in these five registers are sampled and saved by the hardware only when both USER_IV_EN
(HASH_CONTROL_1[5]) and START_INIT_BIT (HASH_CONTROL_1[4]) are high. Since USER_IV_EN and
START_INIT_BIT are automatically cleared by hardware, these five registers do not need to be cleared after they
are used.
HASH_PRE_MSG_LENG_HIGH & HASH_PRE_MSG_LENG_LOW
In contrast to HASH_IV_1 ~ HASH_IV_5, these two registers always affect the hardware. Therefore, they must be
set to zero when “Pre-message length” is not used.
NOTE:
The unit is bit.
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