Samsung S5PC110, Руководство пользователя

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S5PC110_UM 1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER
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1.6.1.5 UART Tx/Rx Status Register
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UTRSTAT0, R, Address = 0xE290_0010
•
UTRSTAT1, R, Address = 0xE290_0410
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UTRSTAT2, R, Address = 0xE290_0810
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UTRSTAT3, R, Address = 0xE290_0C10
There are four UART Tx/Rx status registers in the UART block, namely, UTRSTAT0, UTRSTAT1, UTRSTAT2 and
UTRSTAT3.
UTRSTATn Bit Description Initial State
Reserved [31:3] Reserved 0
Transmitter empty [2] This bit is automatically set to 1 if the transmit buffer register has
no valid data to transmit, and the transmit shift register is empty.
0 = Not empty
1 = Transmitter (which includes transmit buffer and shifter register)
empty 1
Transmit buffer
empty [1] This bit is automatically set to 1 if transmit buffer register is empty.
0 = Buffer register is not empty
1 = Buffer register is empty (In Non-FIFO mode, Interrupt or DMA
is requested.
In FIFO mode, Interrupt or DMA is requested, if Tx
FIFO Trigger Level is set to 00 (Empty))
If UART uses FIFO, check Tx FIFO Count bits and Tx FIFO Full bit
in UFSTAT register instead of this bit. 1
Receive buffer
data ready [0] This bit is automatically set to 1 if receive buffer register contains
valid data, received over the RXDn port.
0 = Buffer register is empty
1 = Buffer register has a received data
(In Non-FIFO mode, Interrupt or DMA is requested)
If UART uses the FIFO, check Rx FIFO Count bits and Rx FIFO
Full bit in UFSTAT register instead of this bit. 0