Samsung S5PC110, Руководство пользователя

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S5PC110_UM 1 DRAM CONTROLLER
1-1
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DRAM CONTROLLER
1.1 OVERVIEW OF DRAM CONTROLLER
1.1.1 INTRODUCTION OF DRAM CONTROLLER
The DRAM controller is an Advanced Microcontroller Bus Architecture (AMBA
tm
) AXI compliant slave to interface
external JEDEC DDR-type SDRAM devices.
To support high-speed memory devices, the DRAM controller uses a SEC DDR PHY interface. The controller
includes an advanced embedded scheduler to utilize memory device efficiently and an optimized pipeline stage to
minimize latency. S5PC110 has two independent DRAM Controllers and Ports, namely, DMC0 and DMC1.
1.1.2 KEY FEATURES OF DRAM CONTROLLER
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Compatible with JEDEC DDR2, low power DDR and low power DDR2 SDRAM specification
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Uses the SEC LPDDR2 PHY interface to support high-speed memory devices
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Supports up to two external chip selects and 1/2/4/8 banks per one chip
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Supports 128 Mb, 256 Mb, 512 Mb, 1 Gb, 2 Gb and 4 Gb density Memory Devices
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Supports 16/ 32-bit wide memory data width
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Optimized pipeline stage for low latency
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Supports QoS scheme to ensure low latency for some applications
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Advanced embedded scheduler enables out-of order operations to utilize memory device efficiently
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Supports excellent chip/bank interleaving and memory interrupting
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Supports AMBA AXI low power channel for systematic power control
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Adapts to various low power schemes to reduce the dynamic and static current of memory
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Supports outstanding exclusive accesses
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Supports bank selective precharge policy