Renesas SH7124 R5F7124, Руководство по оборудованию

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Section 7 User Break Controller (UBC)
Rev. 3.00 Sep. 27, 2007 Page 117 of 758
REJ09B0243-0300
Bit Bit Name
Initial
Value
R/W Description
31 to 0 BAMA31 to
BAMA 0
All 0 R/W Break Address Mask A
Specify bits masked in the channel A break address bits
specified by BARA (BAA31 to BAA0).
0: Break address bit BAAn of channel A is included in
the break condition
1: Break address bit BAAn of channel A is masked and
is not included in the break condition
Note: n = 31 to 0
7.2.3 Break Bus Cycle Register A (BBRA)
BBRA is a 16-bit readable/writable register, which specifies (1) bus master for I bus cycle, (2) L
bus cycle or I bus cycle, (3) instruction fetch or data access, (4) read or write, and (5) operand size
in the break conditions of channel A.
Bit:
Initial value:
R/W:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
- - - - - CPA[2:0] CDA[1:0] IDA[1:0] RWA[1:0] SZA[1:0]
Bit Bit Name
Initial
Value
R/W Description
15 to 11

All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
10 to 8 CPA[2:0] 000 R/W Bus Master Select A for I Bus
Select the bus master when the I bus is selected as the
bus cycle of the channel A break condition. However,
when the L bus is selected as the bus cycle, the setting
of the CPA2 to CPA0 bits is disabled.
000: Condition comparison is not performed
xx1: The CPU cycle is included in the break condition
x1x: Setting prohibited
1xx: Setting prohibited