Section 15 Pin Function Controller (PFC)
Rev. 3.00 Sep. 27, 2007 Page 527 of 758
REJ09B0243-0300
SH7124:
•
Port A Control Register L4 (PACRL4)
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bit Bit
Name
Initial
Value
R/W Description
15 to 0
All
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
•
Port A Control Register L3 (PACRL3)
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R
R/W
R/W
R/W
-
-
-
-
-
-
-
-
-
PA9
MD2
PA9
MD1
PA9
MD0
-
PA8
MD2
PA8
MD1
PA8
MD0
Bit Bit
Name
Initial
Value
R/W Description
15 to 7
All
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
6
5
4
PA9MD2
PA9MD1
PA9MD0
0
0
0
R/W
R/W
R/W
PA9 Mode
Select the function of the
PA9/TCLKD/TXD2/TDO/
POE8
pin. When the E10A is
in use (
ASEMD0
= low), function is fixed to TDO
output.
000: PA9 I/O (port)
001: TCLKD input (MTU2)
110: TXD2 output (SCI)
111:
POE8
input (POE)
Other than above: Setting prohibited
3
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Содержание SH7124 R5F7124
Страница 2: ...Rev 3 00 Sep 27 2007 Page ii of xx ...
Страница 8: ...Rev 3 00 Sep 27 2007 Page viii of xx ...
Страница 36: ...Section 1 Overview Rev 3 00 Sep 27 2007 Page 16 of 758 REJ09B0243 0300 ...
Страница 68: ...Section 2 CPU Rev 3 00 Sep 27 2007 Page 48 of 758 REJ09B0243 0300 ...
Страница 108: ...Section 5 Exception Handling Rev 3 00 Sep 27 2007 Page 88 of 758 REJ09B0243 0300 ...
Страница 166: ...Section 7 User Break Controller UBC Rev 3 00 Sep 27 2007 Page 146 of 758 REJ09B0243 0300 ...
Страница 400: ...Section 9 Multi Function Timer Pulse Unit 2 MTU2 Rev 3 00 Sep 27 2007 Page 380 of 758 REJ09B0243 0300 ...
Страница 724: ...Section 20 List of Registers Rev 3 00 Sep 27 2007 Page 704 of 758 REJ09B0243 0300 ...
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Страница 782: ...SH7125 Group SH7124 Group Hardware Manual ...