Section 8 Bus State Controller (BSC)
Rev. 3.00 Sep. 27, 2007 Page 150 of 758
REJ09B0243-0300
period is required because Iclk
≥
Bclk
≥
Pclk. In the case shown in figure 8.3, where n
=
0 and m
=
1, the period required for access by the CPU is 3
×
Iclk
+
2
×
Bclk
+
2
×
Pclk
+
2
×
Iclk.
Iclk
L bus
Bclk
I bus
Pclk
Peripheral bus
Figure 8.3 Timing of Read Access to the Peripheral Bus (Iclk:Bclk:Pclk = 4:2:1)
Содержание SH7124 R5F7124
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