Renesas SH7124 R5F7124, Руководство по оборудованию

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Section 17 Flash Memory
Rev. 3.00 Sep. 27, 2007 Page 616 of 758
REJ09B0243-0300
(3) Erasing Procedure in User Program Mode
The procedures for download, initialization, and erasing are shown in figure 17.12.
Start erasing procedure
program
Select on-chip program
to be downloaded and
set download destination
by FTDAR
Set FKEY to H'A5
After clearing VBR,
set SCO to 1 and
execute download
DPFR = 0?
Yes
No
Download error processing
Set the FPEFEQ and
FUBRA parameters
Initialization
JSR FTDAR s 32
Yes
End erasing
procedure program
FPFR = 0 ?
No
Initialization error processing
Clear FKEY to 0
Set FEBS parameter
Erasing
JSR FTDAR s 16
Yes
FPFR = 0 ?
No
Clear FKEY and erasing
error processing
Yes
Required block
erasing is
completed?
No
Set FKEY to H'5A
Clear FKEY to 0
(3.1)
(3.2)
(3.3)
(3.4)
(3.5)
(3.6)
1
1
Download
Initialization
Erasing
Figure 17.12 Erasing Procedure
The details of the erasing procedure are described below. The procedure program must be
executed in an area other than the user MAT to be erased.
Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in
on-chip RAM.
Specify 1/4 (initial value) as the frequency division ratios of an internal clock (I
φ
), a bus clock
(B
φ
), and a peripheral clock (P
φ
) through the frequency control register (FRQCR).
After the programming/erasing program has been downloaded and the SCO bit is cleared to 0,
the setting of the frequency control register (FRQCR) can be changed to the desired value. For
the downloaded on-chip program area, see the RAM map for programming/erasing in figure
17.10.