Renesas SH7124 R5F7124, Руководство по оборудованию

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Section 4 Clock Pulse Generator (CPG)
CPGS301C_000020030900
Rev. 3.00 Sep. 27, 2007 Page 55 of 758
REJ09B0243-0300
Section 4 Clock Pulse Generator (CPG)
This LSI has a clock pulse generator (CPG) that generates an internal clock (I
φ
), a bus clock (B
φ
),
a peripheral clock (P
φ
), and a clock (MP
φ
) for the MTU2 module. The CPG also controls power-
down modes.
4.1 Features
•
Five clocks generated independently
An internal clock (I
φ
) for the CPU; a peripheral clock (P
φ
) for the on-chip peripheral modules;
a bus clock (B
φ
= CK) for the external bus interface; and a MTU2 clock (MP
φ
) for the on-chip
MTU2 module.
•
Frequency change function
Frequencies of the internal clock (I
φ
), bus clock (B
φ
), peripheral clock (P
φ
), and MTU2 clock
(MP
φ
) can be changed independently using the divider circuit within the CPG. Frequencies are
changed by software using the frequency control register (FRQCR) setting.
•
Power-down mode control
The clock can be stopped in sleep mode and standby mode and specific modules can be
stopped using the module standby function.
•
Oscillation stop detection
If the clock supplied through the clock input pin stops for any reason, the timer pins can be
automatically placed in the high-impedance state.