Renesas SH7124 R5F7124, Руководство по оборудованию

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Section 8 Bus State Controller (BSC)
Rev. 3.00 Sep. 27, 2007 Page 148 of 758
REJ09B0243-0300
Access to the on-chip RAM for read/write is synchronized with I
φ
clock and is executed in one
clock cycle. For details, see section 18, RAM.
8.4 Access to on-chip Peripheral I/O Register
The on-chip peripheral I/O register is accessed by the bus state controller (BSC) as described in
table 8.2.
Table 8.2 Connection Bus Width of on-chip Peripheral Module and the Number of Access
Cycles
On-chip Peripheral
Module
INTC UBC MTU2 POE2 WDT SCI ADC CMT
PFC,
Port
Connection Bus
Width 16 16 16 16 16 8 16 16 16
Write (3
+
n)
×
Iclk
+
(1
+
m)
×
Bclk
+
2
×
Pclk Number of
Access
Cycles
Read (3
+
n)
×
Iclk
+
(1
+
m)
×
Bclk
+
2
×
Pclk
+
2
×
Iclk
Note: When m
=
0 to 3, Bclk:Pclk
=
4:1
When n
=
0 to 3, lclk:Bclk
=
4:1
When m
=
0, 1, Bclk:Pclk
=
2:1
When n
=
0, 1, lclk:Bclk
=
2:1
When m
=
0, Bclk:Pclk
=
1:1
When n
=
0, lclk:Bclk
=
1:1
This LSI adopts synchronous logic, and data of each bus is input and output in synchronization
with the rising edge of the corresponding clock. The L bus access takes one Iclk cycle, I bus
access takes one Bclk cycle, and peripheral bus access takes two Pclk cycles. When the on-chip
peripheral I/O register is accessed by the CPU, the period required for preparation for data transfer
to the I bus is a period of 3 Iclk cycles.
Figure 8.1 shows an example of timing of write access to the peripheral bus when Iclk:Bclk:Pclk =
4:1:1. From the L bus, to which the CPU is connected, data is output in synchronization with Iclk.
Since there are four Iclk cycles in a single Bclk cycle when Iclk:Bclk = 4:1, data can be output
onto the L bus in four possible timings within one Bclk cycle. Accordingly, a maximum of four
Iclk cycles of period (four Iclk cycles in the example shown in the figure) is required before the
rising edge of Bclk, on which data is transferred from the L bus to the I bus. Because of this, data
is transferred from the L bus to the I bus in a period of (3 + n)
×
Iclk (n = 0 to 3) when Iclk:Bclk =
4:1. The relation of the timing of data output to the L bus and the rising edge of Bclk depends on
the state of program execution. In the case shown in figure 8.1, where Bclk = Pclk = 1:1, the
period required for access by the CPU is (3 + n)
×
Iclk + 1
×
Bclk + 2
×
Pclk.