-
79
-
[FL
low
speed
operation]
[FH
low
speed
operation]
[High
speed
operation]
The
input
logic
of
the
SD
signal
can
be
changed.
If
the
latched
input
is
set
to
accept
input
from
the
SD
signal,
and
if
the
SD
signal
is
OFF
at
the
next
start,
the
latch
will
be
reset.
The
latch
is
also
reset
when
the
latch
input
is
set
to
zero.
When
the
input
filter
is
OFF
the
minimum
pulse
time
for
the
SD
signal
is
two
reference
clock
cycles
(0.1
µ
s).
When
the
input
filter
is
ON,
the
PCL
will
not
respond
to
pulse
signals
shorter
than
the
specified
time.
The
latch
signal
of
the
SD
signal
can
be
monitored
by
reading
SSTSW
(sub
status).
The
SD
signal
terminal
status
can
be
monitored
by
reading
RSTS
(extension
status).
By
reading
the
REST
register,
you
can
check
for
an
error
interrupt
caused
by
the
SD
signal
turning
ON.
Enable/disable
SD
signal
input
<Set
MSDE
(bit
8)
in
PRMD>
0:
Enable
SD
signal
input
1:
Disable
SD
signal
input
[RMD]
(WRITE)
15
8
-
-
-
-
-
-
-
n
Input
logic
of
the
SD
signal
<Set
SDL(bit
6)
in
RENV1>
0:
Negative
logic
1:
Positive
logic
[RENV1]
(WRITE)
7
0
-
n
-
-
-
-
-
-
Set
the
operation
pattern
when
the
SD
signal
is
turned
ON
<Set
SDM
(bit
4)
in
RENV1>
0:
Decelerates
on
receiving
the
SD
signal
and
feeds
at
FL
low
speed
1:
Decelerates
and
stops
on
receiving
the
SD
signal
[RENV1]
(WRITE)
7
0
-
-
-
n
-
-
-
-
Select
the
SD
signal
input
type
<Set
SDLT
(bit
5)
in
RENV1>
0:
The
SD
signal
is
level
input
1:
The
SD
signal
is
latch
input
(To
release
the
latch,
turn
OFF
the
SD
input
when
next
start
command
is
written
or
select
Level
input.)
[RENV1]
(WRITE)
7
0
-
-
n
-
-
-
-
-
Reading
the
latch
status
of
the
SD
signal
<SSD
(bit
15)
in
SSTSW>
0:
The
SD
latch
signal
is
OFF
1:
The
SD
latch
signal
is
ON
[SSTSW]
(READ)
15
8
n
-
-
-
-
-
-
-
Reading
the
SD
signal
<
SDIN
(bit
14)
in
the
RSTS
register>
0:
The
SD
signal
is
OFF
1:
The
SD
signal
is
ON
[RSTS]
(READ)
15
8
-
n
-
-
-
-
-
-
Reading
the
cause
of
an
when
stopped
by
the
SD
signal
<ESSD
(bit
5)
in
RESET>
1:
Deceleration
stop
caused
by
the
SD
signal
turning
ON
[REST]
(READ)
7
0
-
-
n
-
-
-
-
-
Apply
an
input
filter
to
SD
<Set
FLTR
(bit
26)
in
RENV1>
1:
Apply
a
filter
to
the
±
EL,
SD,
ORG,
ALM
and
INP
input
By
applying
a
filter,
signals
with
a
pulse
length
shorter
than
the
FTM
value
will
be
ignored.
[RENV1]
(WRITE)
31
24
-
-
-
-
-
n
-
-
Select
the
input
filter
characteristics
<Set
FTM
(bits
20,
21)
in
RENV1>
00:
3.2
µ
s
10:
200
µ
s
01:
25
µ
s
11:
1.6
ms
[RENV1]
(WRITE)
23
16
-
-
n
n
-
-
-
-
Содержание PCL6113
Страница 1: ...User s Manual For PCL6113 6123 6143 Pulse Control LSI Nippon Pulse Motor Co Ltd...
Страница 11: ...5 3 Terminal Assignment Diagram 3 1 PCL6113 3 2 PCL6123...
Страница 20: ...14 5 Block Diagram...
Страница 115: ...109 11 Stop timing by error...
Страница 116: ...110 13 External Dimensions 13 1 PCL6113...
Страница 117: ...111 13 2 PCL6123...
Страница 118: ...112 13 3 PCL6143...