-
117
-
Label
Type
Position
Description
Reference
EZL
Register
bit
RENV2
28
Set
the
input
logic
for
the
EZ
signal
(0:
Falling,
1:
Rising)
P41,
54
EZu
Terminal
name
141 U
axis
encoder
Z
phase
signal
(PCL6143) P11
EZx
Terminal
name
47,
48 X
axis
encoder
Z
phase
signal
(PCL6123,
6143)
P11
EZy
Terminal
name
84,
79 Y
axis
encoder
Z
phase
signal
(PCL6123,
6143)
P11
EZz
Terminal
name
110 Z
axis
encoder
Z
phase
signal
(PCL6143) P11
FCHGH
Command
41h
Change
immediately
to
FH
speed
P25
FCHGL
Command
40h
Change
immediately
to
FL
speed
P25
Terminal
name
68
Deceleration
monitor
output
for
the
x
axis
(PCL6123)
P13
Terminal
name
105
Deceleration
monitor
output
for
the
y
axis
(PCL6123)
P13
FLTR
Register
bit
RENV1
26
Apply
input
filter
P39
FSCHH
Command
43h
Accelerate
to
FH
speed
P25
FSCHL
Command
42h
Accelerate
to
FL
speed
P25
FTM0
to
1
Register
bit
RENV1
20-21 Set
a
filter
time
constant
for
+EL,
-EL,
SD,
ORG,
ALM,
and
INP
P39
Terminal
name
67
Acceleration
monitor
output
for
the
x
axis.
(PCL6123)
P13
Terminal
name
104
Acceleration
monitor
output
for
the
y
axis
(PCL6123)
P13
IEND
Register
bit
RENV2
30
Specify
that
the
stop
interrupt
will
be
output.
P41
IF0
Terminal
name
1,
1,
1 CPU-I/F
mode
selection
0
(PCL6113,
6123,
6143) P7
IF1
Terminal
name
2,
2,
2 CPU-I/F
mode
selection
1
(PCL6113,
6123,
6143) P7
IFB
Terminal
name
13,
14,
15 Busy
CPU-I/F
(PCL6113,
6123,
6143) P8
INP
Terminal
name
41
In-position
input
(PCL6113)
P10
INPL
Register
bit
RENV1
22
Select
input
logic
of
INP
signal
(0:
Negative,
1:
Positive)
P39
INPu
Terminal
name
150 In
position
input
for
the
U
axis
(PCL6143)
P10
INPx
Terminal
name
42,
43 In
position
input
for
the
X
axis
(PCL6123,
6143)
P10
INPy
Terminal
name
79,
74 In
position
input
for
the
Y
axis
(PCL6123,
6143)
P10
INPz
Terminal
name
105 In
position
input
for
the
Z
axis
(PCL6143)
P10
Terminal
name
11,
12,
13 Interrupt
request
signal
P8
INTM
Register
bit
RENV1
29
Mask
the
INT
output
terminal
P39
IOP0
to
7
Sub-status
bits
SSTSW
0-7
Read
the
P0
to
P7
terminal
status.
P25
IOPB
Byte
map
name
Read
the
general
I/O
port
P18
IRC1
Register
bit
RIRQ
6
Enable
an
INT
when
the
Comparator
1
conditions
are
met
P44
IRC2
Register
bit
RIRQ
7
Enable
an
INT
when
the
Comparator
2
conditions
are
met
P44
IRDE
Register
bit
RIRQ
5
Enable
an
INT
when
the
deceleration
is
finished
P44
IRDR
Register
bit
RIRQ
11
Enable
an
INT
when
the
±DR
(PA,
PB)
input
changes
P44
IRDS
Register
bit
RIRQ
4
Enable
an
INT
when
the
deceleration
starts
P44
IREN
Register
bit
RIRQ
0
Enable
an
INT
when
there
is
a
normal
stop
P44
IRLT
Register
bit
RIRQ
8
Enable
an
INT
when
the
count
value
is
latched
by
an
LTC
input
P44
IRNM
Register
bit
RIRQ
1
Enable
an
INT
when
writing
to
the
pre-register
for
operation
is
enabled
P44
IROL
Register
bit
RIRQ
9
Enable
an
INT
when
the
count
value
is
latched
by
an
ORG
input
P44
IRSA
Register
bit
RIRQ
12
Enable
an
INT
by
turning
ON
the
input
P44
IRSD
Register
bit
RIRQ
10
Enable
an
INT
by
turning
ON
the
SD
input
P44
IRUE
Register
bit
RIRQ
3
Enable
an
INT
when
the
acceleration
is
finished
P44
IRUS
Register
bit
RIRQ
2
Enable
an
INT
when
acceleration
starts
P44
ISC1
Register
bit
RIST
6
Comparator
1
conditioned
status
P46
ISC2
Register
bit
RIST
7
Comparator
2
conditioned
status
P46
ISDE
Register
bit
RIST
5
Equals
1
when
deceleration
is
finished
P46
ISDS
Register
bit
RIST
4
Equals
1
when
deceleration
starts
P46
ISEN
Register
bit
RIST
0
Equals
1
when
stopped
automatically
P46
ISLT
Register
bit
RIST
8
Equals
1
when
the
count
value
is
latched
by
an
LTC
input
P46
ISMD
Register
bit
RIST
12
Equals
1
when
a
-DR
input
signal
is
ON.
P47
ISNM
Register
bit
RIST
1
Enable
writing
to
the
pre-register
P46
ISOL
Register
bit
RIST
9
Latched
count
value
from
the
ORG
input
P46
ISPD
Register
bit
RIST
11
Equals
1
when
the
+DR
(PA)
input
is
ON
P47
ISSA
Register
bit
RIST
13
Equals
1
when
the
input
is
ON
P47
ISSD
Register
bit
RIST
10
Equals
1
when
the
SD
input
is
ON
P47
ISUE
Register
bit
RIST
3
Equals
1
when
the
acceleration
is
finished
P46
ISUS
Register
bit
RIST
2
Equals
1
when
to
start
acceleration
P46
LOF1
Register
bit
RENV3
5
Release
the
latch
on
COUNTER1
that
was
triggered
by
an
LTC
input.
P42,
90
LOF2
Register
bit
RENV3
9
Release
the
latch
on
COUNTER2
that
was
triggered
by
an
LTC
input.
P42,
90
LTC
Terminal
name
42
Latch
input
(PCL6113)
P10
LTCH
Command
29h
Substitute
the
LTC
input
(for
counting
or
latching)
P26,
90
LTCL
Register
bit
RENV1
23
Select
the
trigger
edge
for
the
LTC
signal
(0:
Falling
edge,
1:
Rising
edge)
P38,
90
LTCu
Terminal
name
137 Latch
the
input
for
the
U
axis
(PCL6143)
P10
LTCx
Terminal
name
43,
44 Latch
the
input
for
the
X
axis
(PCL6123,
6143)
P10
LTCy
Terminal
name
80,
75 Latch
the
input
for
the
Y
axis
(PCL6123,
6143)
P10
LTCz
Terminal
name
106 Latch
the
input
for
the
Z
axis
(PCL6143)
P10
MADJ
Register
bit
RMD
26
Disable
the
FH
correction
function
P37
MAX0
to
3
Register
bits
RMD
20-23
Specify
the
axis
used
to
control
stopping
for
a
simultaneous
start
P37,
94
MCCE
Register
bit
RMD
11
Stop
counting
output
pulses
on
COUNTER1,
2
P36
MCDE
Register
bit
RMD28
Validate
the
input
P37
MCDO
Register
bit
RMD29
Output
while
selecting
the
FL
speed
P37
Содержание PCL6113
Страница 1: ...User s Manual For PCL6113 6123 6143 Pulse Control LSI Nippon Pulse Motor Co Ltd...
Страница 11: ...5 3 Terminal Assignment Diagram 3 1 PCL6113 3 2 PCL6123...
Страница 20: ...14 5 Block Diagram...
Страница 115: ...109 11 Stop timing by error...
Страница 116: ...110 13 External Dimensions 13 1 PCL6113...
Страница 117: ...111 13 2 PCL6123...
Страница 118: ...112 13 3 PCL6143...