NPM PCL6113, Руководство пользователя

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8-3-23. REST register
Used to check the error interrupt cause. (Read only.)
The corresponding bit will be "1" when that item has caused an error interrupt.
This register is reset when read.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ESPE ESSD ESP0 ESEM ESEE ESSP ESAL ESML ESPL
0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Bit name Description
0 ESPL Stopped by the +EL input being turned ON.
1 ESML Stopped by the -EL input being turned ON.
2 ESAL Stopped by turning the ALM input ON, or when an ALM input occurs while
stopping.
3 ESSP Stopped by the input being turned ON.
4 ESEM Stopped by the input being turned ON, or when an ALM input occurs
while stopping.
5 ESSD Decelerated and stopped by the SD input being turned ON.
6 ESPO An overflow occurred in the PA/PB input buffer counter.
7 ESEE An EA/EB input error occurred. (Does not stop)
8 ESPE A PA/PB input error occurred. (Does not stop)
9 to 31 Not defined (Always set to 0.)
8-3-24. RIST register
This register is used to check the cause of event interruption. (Read only.)
When an event interrupt occurs, the bit corresponding to the cause will be set to 1.
This register is reset when read.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISLT ISDE ISC1 ISDS ISC2 ISUE ISPD ISMD ISSD ISSA ISOL ISUS ISNM ISEN
0 0 0
0 0
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Bit name Description
0 ISEN Stopped automatically.
1 ISNM Available to write operation to the pre-register.
2 ISUS Starting acceleration.
3 ISUE Ending acceleration.
4 ISDS Starting deceleration.
5 ISDE Ending deceleration.
6 ISC1 The comparator 1 conditions were met.
7 ISC2 The comparator 2 conditions were met.
8 ISLT The count value was latched by an LTC input.
9 ISOL The count value was latched by an ORG input.
10 ISSD The SD input turned ON.
11 ISPD The +DR (PA) input changed.
12 ISMD The -DR (PB) input changed.
13 ISSA The input turned ON.
14 to 31 Not defined (Always set to 0.)