NPM PCL6113, Руководство пользователя

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8-3-19. RIRQ register
Enables event interruption cause.
Bits set to 1 that will enable an event interrupt for that event.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IRSA IRDR IROL IRSD IRLT IRDE IRC1 IRDS IRC2 IRUE IRUS IRNM IREN
0 0 0
0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Bit name Description
0 IREN Stopping normally.
1 IRNM When enabled to write to the pre-register.
2 IRUS Starting acceleration.
3 IRUE When ending acceleration.
4 IRDS When starting deceleration.
5 IRDE When ending deceleration.
6 IRC1 When Comparator 1 conditions are met.
7 IRC2 When Comparator 2 conditions are met.
8 IRLT When latching the count value with an LTC signal input.
(When LOF1 = LOF2 = 1 in RENV3, an interrupt will not occur.)
9 IROL When latching the count value with an ORG signal input.
10 IRSD When the SD input is ON.
(Even when the SD input is disabled by setting MSDE = 0 in the PRMD
register, an interrupt will occur.)
11 IRDR When the ±DR (PA,PB) input is changed.
(When = H, the interrupt will not occur.)
12 IRSA When the input is ON.
13 to 31 Not defined (Always set to 0.)
8-3-20. RLTC1 register
Latched data for COUNTER1. (Read only.)
The contents of COUNTER1 are copied when triggered by the LTC, an ORG input, or an LTCH
command.
Data
range: -134,217,728 to +134,217,727
For details about the counters, see section "11-10. Counters."
8-3-21. RLTC2 register
Latched data for COUNTER2 (Read only.)
The contents of COUNTER2 are copied when triggered by the LTC, an ORG input, or an LTCH
command.
Data
range: -134,217,728 to +134,217,727
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
& & & &
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
& & & &