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External Memory Expansion Port (Port A)
2
-8
DSP56303 User’s Manual
BB
Input/
Output
Input
Bus Busy—Indicates that the bus is active and must be asserted and
deasserted synchronous to CLKOUT. Only after BB is deasserted can
the pending bus master become the bus master (and then assert the
signal again). The bus master can keep BB asserted after ceasing bus
activity, regardless of whether BR is asserted or deasserted. This is
called “bus parking” and allows the current bus master to reuse the
bus without re-arbitration until another device requires the bus. BB is
deasserted by an “active pull-up” method (that is, BB is driven high
and then released and held high by an external pull-up resistor).
BB requires an external pull-up resistor.
CAS
Output
Tri-stated
Column Address Strobe—When the DSP is the bus master, DRAM
uses CAS to strobe the column address. Otherwise, if the Bus
Mastership Enable (BME) bit in the DRAM Control Register is cleared,
the signal is tri-stated.
BCLK
Output
Tri-stated
Bus Clock—When the DSP is the bus master, BCLK is active when
the OMR[ATE] is set. When BCLK is active and synchronized to
CLKOUT by the internal PLL, BCLK precedes CLKOUT by one-fourth
of a clock cycle.
BCLK
Output
Tri-stated
Bus Clock Not—When the DSP is the bus master, BCLK is the
inverse of the BCLK signal. Otherwise, the signal is tri-stated.
Table 2-8. External Bus Control Signals (Continued)
Signal
Name
Type
State During Reset,
Stop, or Wait
Signal Description
Содержание DSP56303
Страница 1: ...DSP56303 User s Manual 24 Bit Digital Signal Processor DSP56303UM AD Revision 1 January 2001 ...
Страница 52: ...JTAG OnCE Interface 2 22 DSP56303 User s Manual ...
Страница 114: ...General Purpose Input Output GPIO 5 10 DSP56303 User s Manual ...
Страница 212: ...GPIO Signals and Registers 8 26 DSP56303 User s Manual ...
Страница 268: ...Interrupt Equates A 22 DSP56303 User s Manual ...
Страница 306: ...Programming Sheets B 38 DSP56303 User s Manual ...
Страница 320: ...Index 14 DSP56303 User s Manual ...