Motorola DSP56303, Руководство пользователя

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External Memory Expansion Port (Port A)
Signals/Connections
2 -7
TA Input Ignored Input Transfer Acknowledge—If the DSP56303 is the bus master and
there is no external bus activity, or the DSP56303 is not the bus
master, the TA input is ignored. The TA input is a Data Transfer
Acknowledge (DTACK) function that can extend an external bus cycle
indefinitely. Any number of wait states (1, 2,..., infinity) can be added
to the wait states inserted by the BCR by keeping TA deasserted. In
typical operation, TA is deasserted at the start of a bus cycle, asserted
to enable completion of the bus cycle, and deasserted before the next
bus cycle. The current bus cycle completes one clock period after TA
is asserted synchronous to CLKOUT. The number of wait states is
determined by the TA input or by the Bus Control Register (BCR),
whichever is longer. The BCR can set the minimum number of wait
states in external bus cycles.
To use the TA functionality, the BCR must be programmed to at least
one wait state. A zero wait state access cannot be extended by TA
deassertion; otherwise improper operation may result. TA can operate
synchronously or asynchronously, depending on the setting of the
TAS bit in the Operating Mode Register (OMR).
TA functionality cannot be used during DRAM-type accesses;
otherwise improper operation may result.
BR Output Output
(deasserted) Bus Request—Asserted when the DSP requests bus mastership and
deasserted when the DSP no longer needs the bus. BR can be
asserted or deasserted independently of whether the DSP56303 is a
bus master or a bus slave. Bus “parking” allows BR to be deasserted
even though the DSP56303 is the bus master (see the description of
bus “parking” in the BB signal description). The Bus Request Hold
(BRH) bit in the BCR allows BR to be asserted under software control,
even though the DSP does not need the bus. BR is typically sent to an
external bus arbitrator that controls the priority, parking and tenure of
each master on the same external bus. BR is affected only by DSP
requests for the external bus, never for the internal bus. During
hardware reset, BR is deasserted and the arbitration is reset to the
bus slave state.
BG Input Ignored Input Bus Grant—Must be asserted/deasserted synchronous to CLKOUT
for proper operation. An external bus arbitration circuit asserts BG
when the DSP56303 becomes the next bus master. When BG is
asserted, the DSP56303 must wait until BB is deasserted before
taking bus mastership. When BG is deasserted, bus mastership is
typically given up at the end of the current bus cycle. This may occur
in the middle of an instruction that requires more than one external
bus cycle for execution.
Table 2-8. External Bus Control Signals (Continued)
Signal
Name
Type
State During Reset,
Stop, or Wait
Signal Description