Motorola DSP56303, Руководство пользователя

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DSP56300 Core Functional Blocks
1 -8 DSP56303 User’s Manual
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On-chip memory-expandable hardware stack
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Nested hardware DO loops
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Fast auto-return interrupts
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Hardware system stack
The PCU uses the following registers:
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Program counter register
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Status register
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Loop address register
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Loop counter register
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Vector base address register
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Size register
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Stack pointer
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Operating mode register
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Stack counter register
1.5.4 PLL and Clock Oscillator
The clock generator in the DSP56300 core comprises two main blocks: the PLL, which
performs clock input division, frequency multiplication, and skew elimination; and the clock
generator, which performs low-power division and clock pulse generation. These features
allow you to:
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Change the low-power divide factor without losing the lock
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Output a clock with skew elimination
The PLL allows the processor to operate at a high internal clock frequency using a
low-frequency clock input, a feature that offers two immediate benefits:
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A lower-frequency clock input reduces the overall electromagnetic interference
generated by a system.
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The ability to oscillate at different frequencies reduces costs by eliminating the need to
add additional oscillators to a system.