Intel 8XC196NT, Руководство пользователя

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2-1
CHAPTER 2
ARCHITECTURAL OVERVIEW
The 16-bit 8XC196NT CHMOS microcontroller is designed to handle high-speed calculations
and fast input/output (I/O) operations. It shares a common architecture and instruction set with
other members of the MCS
®
96 microcontroller family. This device extends the addressability of
the MCS 96 family to 1 Mbyte. This chapter provides a high-level overview of the architecture.
2.1 TYPICAL APPLICATIONS
MCS 96 microcontrollers are typically used for high-speed event control systems. Commercial
applications include modems, motor-control systems, printers, photocopiers, air conditioner con-
trol systems, disk drives, and medical instruments. Automotive customers use MCS 96 microcon-
trollers in engine-control systems, airbags, suspension systems, and antilock braking systems
(ABS).
2.2 DEVICE FEATURES
Table 2-1 lists the features of the 8XC196NT.
2.3 BLOCK DIAGRAM
Figure 2-1 shows the major blocks within the device. The core of the device (Figure 2-2) consists
of the central processing unit (CPU) and memory controller. The CPU contains the register file
and the register arithmetic-logic unit (RALU). The CPU connects to both the memory controller
and an interrupt controller via a 16-bit internal bus. An extension of this bus connects the CPU to
the internal peripheral modules. In addition, an 8-bit internal bus transfers instruction bytes from
the memory controller to the instruction register in the RALU.
Table 2-1. Features of the 8XC196NT
Device Pins
OTPROM
(Note 1)
Register
RAM
(Note 2)
Code/Data
RAM
I/O
Pins
EPA
Pins
SIO/
SSIO
Ports
A/D
Channels
External
Interrupt
Pins
8XC196NT 68 32 K 1024 512 56 10 2 4 1
NOTES:
1.
Nonvolatile memory is optional. The second character of the device name indicates the presence
and type of nonvolatile memory. 80C196NT = none; 87C196NT = OTPROM.
2. Register RAM amount includes the 24 bytes allocated to core SFRs and the stack pointer.