Intel 8XC196NT, Руководство пользователя

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8XC196NT USER’S MANUAL
14-2
14.2 EXTERNAL MEMORY INTERFACE SIGNALS
Table 14-2 describes the external memory interface signals. For some signals, the pin has an al-
ternate function (shown in the Multiplexed With column). In some cases the alternate function is
a port signal (e.g., P2.7). Chapter 6, “I/O Ports,” describes how to configure a pin for its I/O port
function and for its special function. In other cases, the signal description includes instructions
for selecting the alternate function.
Table 14-2. External Memory Interface Signals
Function
Name
Type Description
Multiplexed
With
A19:16 I/O Address Lines 16–19
These address lines provide address bits 16–19 during the entire
external memory cycle, supporting extended addressing of the
1 Mbyte address space.
NOTE: Internally, there are 24 address bits; however, only 20
address lines (A19:16 and AD15:0) are bonded out. The
internal address space is 16 Mbyte (000000–FFFFFFH)
and the external address space is 1 Mbyte (00000–
FFFFFH). The device resets to FF2080H in internal ROM
or
x F2080H in external memory.
A19:16 are multiplexed with EPORT.3:0.
EPORT.3:0
AD15:0 I/O Address/Data Lines
These pins provide a multiplexed address and data bus. During the
address phase of the bus cycle, address bits 0–15 are presented on
the bus and can be latched using ALE or ADV#. During the data
phase, 8- or 16-bit data is transferred. When a bus access is not
occurring, these pins revert to their I/O port function.
P4.7:0
P3.7:0
ADV# O Address Valid
This active-low output signal is asserted only during external
memory accesses. ADV# indicates that valid address information is
available on the system address/data bus. The signal remains low
while a valid bus cycle is in progress and is returned high as soon as
the bus cycle completes.
An external latch can use this signal to demultiplex the address from
the address/data bus. A decoder can also use this signal to generate
chip selects for external memory.
P5.0/ALE
ALE O Address Latch Enable
This active-high output signal is asserted only during external
memory cycles. ALE signals the start of an external bus cycle and
indicates that valid address information is available on the system
address/data bus. ALE differs from ADV# in that it does not remain
active during the entire bus cycle.
An external latch can use this signal to demultiplex the address from
the address/data bus.
P5.0/ADV#