Intel 8XC196NT, Руководство пользователя

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8XC196NT USER’S MANUAL
12-8
Figure 12-5. External Clock Connections
Figure 12-6. External Clock Drive Waveforms
At power-on, the interaction between the internal amplifier and its feedback capacitance (i.e., the
Miller effect) may cause a load of up to 100 pF at the XTAL1 pin if the signal at XTAL1 is weak
(such as might be the case during start-up of the external oscillator). This situation will go away
when the XTAL1 input signal meets the V
IL
and V
IH
specifications (listed in the datasheet). If
these specifications are met, the XTAL1 pin capacitance will not exceed 20 pF.
12.5 RESETTING THE DEVICE
Reset forces the device into a known state. As soon as RESET# is asserted, the I/O pins, the con-
trol pins, and the registers are driven to their reset states. (Table B-6 on page B-14 lists the reset
states of the pins. See Table C-2 on page C-2 for the reset values of the SFRs.) The device re-
mains in its reset state until RESET# is deasserted. When RESET# is deasserted, the bus control-
ler fetches the chip configuration bytes (CCBs), loads them into the chip configuration registers
(CCRs), and then fetches the first instruction.
4.7 k
Ω
†
8XC196 Device
XTAL2
XTAL1
External
Clock Input
Clock Driver
No Connection
VCC
A0274-02
†
Required if TTL driver is used. Not needed if CMOS driver is used.
4.7 k
Ω
†
8XC196 Device
XTAL2
XTAL1
External
Clock Input
Clock Driver
No Connection
VCC
A0274-02
†
Required if TTL driver is used. Not needed if CMOS driver is used.
A2119-02
T
XHXX
T
XLXX
T
XHXL
T
XLXL
0.3 V
CC
– 0.5 V
0.7 V
CC
+ 0.5 V
T
XLXH
0.7 V
CC
+ 0.5 V
0.3 V
CC
– 0.5 V