Intel 8XC196NT, Руководство пользователя

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8XC196NT USER’S MANUAL
14-22
14.6.2 Disabling the Bus-hold Protocol
To disable hold requests, clear WSR.7. The device does not take control of the bus immediately
after HLDEN is cleared. Instead, it waits for the current HOLD# request to finish and then dis-
ables the bus-hold feature and ignores any new requests until the bit is set again.
Sometimes it is important to prevent another device from taking control of the bus while a block
of code is executing. One way to protect a code segment is to clear WSR.7 and then execute a
JBC instruction to check the status of the HLDA# signal. The JBC instruction prevents the RALU
from executing the protected block until current HOLD# requests are serviced and the hold fea-
ture is disabled. This is illustrated in the following code:
DI ;Disable interrupts to prevent
;code interruption
PUSH WSR ;Disable hold requests and
LDB WSR,#1FH ;window Port 2
WAIT: JBC P2_PIN,6, WAIT ;Check the HLDA# signal. If set,
;add protected instruction here
POP WSR ;Enable hold requests
EI ;Enable interrupts
14.6.3 Hold Latency
When an external device asserts HOLD#, the device finishes the current bus cycle and then as-
serts HLDA#. The time it takes the device to assert HLDA# after the external device asserts
HOLD# is called hold latency (see Figure 14-9). Table 14-5 lists the maximum hold latency for
each type of bus cycle.
14.6.4 Regaining Bus Control
While HOLD# is asserted, the device continues executing code until it needs to access the exter-
nal bus. If executing from internal memory, it continues until it needs to perform an external
memory cycle. If executing from external memory, it continues executing until the queue is emp-
ty or until it needs to perform an external data cycle. As soon as it needs to access the external
bus, the device asserts BREQ# and waits for the external device to deassert HOLD#. After assert-
ing BREQ#, the device cannot respond to any interrupt requests, including NMI, until the exter-
nal device deasserts HOLD#. One state time after HOLD# goes high, the device deasserts
HLDA# and, with no delay, resumes control of the bus.
Table 14-5. Maximum Hold Latency
Bus Cycle Type
Maximum Hold Latency
(state times)
Internal execution or idle mode 1.5
16-bit external execution 2.5 + 1 per wait state
8-bit external execution 2.5 + 2 per wait state