![Intel 8XC196NT Скачать руководство пользователя страница 150](http://html1.mh-extra.com/html/intel/8xc196nt/8xc196nt_user-manual_2072210150.webp)
6-1
CHAPTER 6
I/O PORTS
I/O ports provide a mechanism to transfer information between the device and the surrounding
system circuitry. They can read system status, monitor system operation, output device status,
configure system options, generate control signals, provide serial communication, and so on.
Their usefulness in an application is limited only by the number of I/O pins available and the
imagination of the engineer.
6.1
I/O PORTS OVERVIEW
Standard I/O port registers are located in the SFR address space and they can be windowed. Mem-
ory-mapped I/O port registers are located in memory-mapped address space. Memory-mapped
registers must be accessed with indirect or indexed addressing; they cannot be windowed. All
ports can provide low-speed input/output pins or serve alternate functions. Table 6-1 provides an
overview of the device I/O ports. The remainder of this chapter describes the ports in more detail
and explains how to configure the pins. The chapters that cover the associated peripherals discuss
using the pins for their special functions.
6.2
INPUT-ONLY PORT 0
Port 0 is a four-bit, high-impedance, input-only port. Its pins can be read as digital inputs; they
are also inputs to the A/D converter. Port 0 differs from the other ports in that its pins can be used
only as inputs to the digital or analog circuitry.
Because port 0 is permanently configured as an input-only port, it has no configuration registers.
Its single register, P0_PIN, can be read to determine the current state of the pin. The register is
byte-addressable and can be windowed. (See “Windowing” on page 4-15)
Table 6-1. Device I/O Ports
Port
Bits
Type
Direction
Associated Peripheral(s)
Port 0
4
Standard
Input-only
A/D converter
Port 1
8
Standard
Bidirectional
EPA and timers
Port 2
8
Standard
Bidirectional
SIO, interrupts, bus control, clock gen.
Port 3
8
Memory-mapped
Bidirectional
Address/data bus
Port 4
8
Memory-mapped
Bidirectional
Address/data bus
Port 5
8
Memory-mapped
Bidirectional
Bus control, slave port
Port 6
8
Standard
Bidirectional
EPA, SSIO
EPORT
4
Memory-mapped
Bidirectional
Extended address lines
Содержание 8XC196NT
Страница 1: ...8XC196NT Microcontroller User s Manual...
Страница 2: ...8XC196NT Microcontroller User s Manual June 1995 Order Number 272317 003...
Страница 22: ...1 Guide to This Manual...
Страница 23: ......
Страница 35: ......
Страница 36: ...2 Architectural Overview...
Страница 37: ......
Страница 49: ......
Страница 50: ...3 Programming Considerations...
Страница 51: ......
Страница 66: ...4 Memory Partitions...
Страница 67: ......
Страница 104: ...5 Standard and PTS Interrupts...
Страница 105: ......
Страница 147: ......
Страница 148: ...6 I O Ports...
Страница 149: ......
Страница 176: ...7 Serial I O SIO Port...
Страница 177: ......
Страница 194: ...8 Synchronous Serial I O SSIO Port...
Страница 195: ......
Страница 211: ......
Страница 212: ...9 Slave Port...
Страница 213: ......
Страница 231: ......
Страница 232: ...10 Event Processor Array EPA...
Страница 233: ......
Страница 270: ...11 Analog to digital Converter...
Страница 271: ......
Страница 291: ......
Страница 292: ...12 Minimum Hardware Considerations...
Страница 293: ......
Страница 306: ...13 Special Operating Modes...
Страница 307: ......
Страница 317: ......
Страница 318: ...14 Interfacing with External Memory...
Страница 319: ......
Страница 362: ...15 Programming the Nonvolatile Memory...
Страница 363: ......
Страница 408: ...A Instruction Set Reference...
Страница 409: ......
Страница 476: ...B Signal Descriptions...
Страница 477: ......
Страница 493: ......
Страница 494: ...C Registers...
Страница 495: ......
Страница 565: ......
Страница 566: ...Glossary...
Страница 567: ......
Страница 580: ...Index...
Страница 581: ......
Страница 597: ......