IBM 3745 Series, Справочник по техническому обслуживанию оборудования

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TIC Bus Interconnection Control
The TIC interconnection control provides a mechanism for transferring data between TIC storage (RAM)
and CCU storage, via cycle steal. It operates in halfword bus mode.
The function performed by the TIC bus interconnection control can be visualized as a double interface
DMA controller with a 128-byte hardware store-and-forward buffer. The 128-byte buffer can logically
connect either to the TIC bus interconnection control or to the local bus, but not to both at the same time.
When DMA data transfer is occurring at the TIC bus interconnection control, the TIC is the bus master,
and the data can flow in only one direction (read or write) at a time.
In addition to its DMA function, the TIC bus interconnection control can also transfer data to or from TIC
storage.
This function is intended for adapter initialization and to obtain TIC status.
Receive Operation
On receive, data is taken from the ring into the front end, where it is reshaped into distortion-free digital
signaling elements.
The front end synchronizes itself with the received data stream and develops a clock which is boundary-
aligned to the bit stream.
This bit stream, along with the derived clock, is passed to the protocol handler.
The protocol handler converts the encoded data stream into coding usable by the adapter.
By counting received clock pulses, the protocol handler assembles the bit stream into halfwords units.
Parity is generated on the received data de-serialized from the ring to check data validity through the
adapter.
During the receive sequence, cyclic redundancy check (CRC) calculation is begun on the received data.
The destination address is compared against the stored values in the protocol handler to determine if the
message is to be copied by the adapter. If so, the protocol handler conditions itself to begin the copy, and
transfer is started to the message processor.
The destination and source addresses, the physical control field, the data portions, and the CRC charac-
ters of the in-progress received message are now passed to the message processor in sequence.
When the end of the CRC-protected field is received, the previously received CRC characters are com-
pared to the calculated CRC.
Ÿ If there is a match, message reception is considered complete by the protocol handler.
Ÿ
If there is a mismatch on the CRC check, the message processor is signalled that the message should
not be considered valid.
The message processor assembles into multi-byte blocks the information received from the protocol
handler.
When that assembly is complete, the message processor begins a transfer into CCU storage. These
segment transfers continue until the complete message has been transferred.
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IBM 3745 Models 130, 150, 160, 170, and 17A: Hardware Maintenance Reference