IBM 3745 Series, Справочник по техническому обслуживанию оборудования

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DMA Bus Errors Reported by the FESH
They are reported by the FESH through a level 2
interrupt and then both interface are disabled by the microcode.
:
The CSP microcode fills the LCS field
of the PSA status with a status byte telling the reason for the error (Refer to “Line Communication Status
(LCS)” on page 5-31 and “Extended Line Communication Status (ELCS) (Initial Status=B'110') for HSS”
on page 5-35 for code description).
The microcode then raises CCU level 2 interrupt.
Line interfaces are started again by the CSP microcode when the NCP sends the proper SDLC command
sequence.
CSP Interconnection Errors
The CSP communicates with the FESH through the external registers located in the FESH (register range
X'0D' to X'17').
The FESH completes the operation with the 'acknowledge' signal to the CSP if no error conditions were
detected.
The FESH monitors the CSP interconnection for the following errors:
Ÿ Interconnection error signal from the CSP
Ÿ Bidirectional cycle steal data bus parity error
Ÿ
External register address and select out parity error
Ÿ
Data out odd parity error during an external register write operation.
Ÿ External register address invalid.
If an error occurs in the external register address because of a parity error or because the external reg-
ister does not exist in the FESH, the 'acknowledge' signal is not sent to the CSP.
Also, if the data bus parity is incorrect during an external register write, the 'acknowledge' signal is not
sent to the CSP.
When 'acknowledge' is not returned to the CSP by the FESH, the CSP sets the adapter interconnection
check bit ON (external register X'03' bit 6 = 1) and terminates the operation.
The FESH does not report any error condition.
Parity errors occurring on the cycle steal interconnection can be detected by the FESH or by the CSP.
If the FESH detects a parity error on the data bus during a cycle steal write, the FESH sets a level 2
interrupt to the CSP with the CSP interconnection error bit ON (external register X'10' bit 3=1) after com-
pleting the operation.
The parity checking on the cycle steal address bus and the CSP data bus during a cycle steal or external
register read operation is performed by the CSP.
When the CSP detects a parity error, the CSP sets the adapter interconnection check in CSP register
X'03' and activates the 'cycle steal error' line.
When the FESH detects this signal, the cycle steal operation ceases and the FESH activates a level 2
interrupt to the CSP.
The CSP interconnection error bit is set ON in FESH external register X'10'.
Detection of this error causes a level 2 interrupt to the CSP.
Chapter 5. High Performance Transmission Subsystem (HPTSS)
5-27