IBM 3745 Series, Справочник по техническому обслуживанию оборудования

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Before the swap
Physical addresses ð 1 2 3 4 5 6 7
┌──────┬─────┬─────┬─────┬─────┬─────┬─────┬─────┬─────┐
│ DMUX │ LIC │ LIC │ LIC │ LIC │ LIC │ LIC │ LIC │ LIC │
│ card │
A │ B │ C │ D │ E │ F │ G │ H │
└──────┴─────┴─────┴─────┴─────┴─────┴─────┴─────┴─────┘
Logical addresses ð 1 2 3 4 5 6 7
After the swap
Physical addresses ð 1 2 3 4 5 6 7
┌──────┬─────┬─────┬─────┬─────┬─────┬─────┬─────┬─────┐
│ DMUX │ LIC │ LIC │ LIC │ LIC │ LIC │ LIC │ LIC │ LIC │
│ card │
A │ B │ C │ D │ E │ F │ G │ H │
└──────┴─────┴─────┴─────┴─────┴─────┴─────┴─────┴─────┘
Logical addresses '7' 1 2 3 4 5 6 'ð'
After the swap, on the serial link, LICA takes the slots of LICH and LICH takes the
slots of LICA.
LIC Address Register Contents
Write mode Read mode
Bits Meaning Bits Meaning
0 LIC logical address bit 0 0 LIC wired address bit 0
1 LIC logical address bit 1 1 LIC wired address bit 1
2 LIC logical address bit 2 2 LIC wired address bit 2
3 Enable/disable logical add 3 Not used
4 Not used 4 EC number
5 Not used 5 EC number
LIC Control Register
The LIC control register X'02' bit 1 and bit 3 (Line enable E0 and E1) controls the
swapping.
Bits Meaning
0 High-speed line
1 Line enable E0
2 X.21 CCITT used by FESA 80
3 Line enable E1
4 Not used
5 Transmit bit echo
Enable Clock Mode
Register X'03' bits 4 and 5 select the clock mode. They are OFF after a reset
command (that is 00 = diag mode).
There is no clock until the enable clock mode bit is set, except if the LIC detects
that the cable ID is a local attach cable.
After the reset the LIC forces the local attach clock mode: 11 (speed given by ICF
after reset: 2400 bps).
Chapter 4. Transmission Subsystem (TSS)
4-47