FESA Inbound and Outbound Control RAMs
The control RAMs contain all the information required by the FES and the microcode to manage the
lines.
:
The control RAMs are divided into 32 areas. Each area stores the contents of the MUX/LIC
registers associated to one line.
FESA Inbound/Outbound RAMs Addressing
The CSP microcode uses two CSP external registers (X'13' and X'15') to access the outbound and
inbound RAMs,
The FESA external registers are located in the outbound and inbound RAMs. The following tables show
the bits of registers X'13' and X'15' used to access the FESA inbound and outbound RAMs.
X'13': Line Interface Address
X'15': Asynchronous Operation Command
Local Store 6 (CHHITMIO Input)
FESA Inbound/Outbound RAM Layout
FESA control register bit 5, controls the type of opera-
tion:
OFF
Write or output operation
ON
Read or input operation.
Bits
Functions
0 0 . .
. . . .
Not used, always 00
. . x x
x . . .
Card address
. . . .
. x x .
Line address
. . . .
. . . Z
See 'FESA inbound/outbound RAM layout'
Bits
Functions
x . . .
. . . .
OFF = read, ON = write
. x x .
. . . .
External
. . . I
RR . .
See 'FESA Inbound/Outbound RAM layout'
Bits
Functions
x . . .
. . . .
OFF = read, ON = write
. . x .
. . . .
OFF = outbound RAM, ON = inbound RAM
. . . I
RREZ
See 'FESA Inbound/Outbound RAM Layout'
Chapter 4. Transmission Subsystem (TSS)
4-29
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