Emerson Affinity, Руководство пользователя

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218
Affinity User Guide
www.controltechniques.com Issue Number: 5
Pr 14.07 defines the time taken for the reference input to ramp from 0 to
100% following a 0 to 100% step change in input.
PID 1 is enabled when Pr 14.08 = 1 and both the parameter sources
defined by Pr 14.09 and Pr 14.27 have a value of one. (The source value
for Pr 14.09 or Pr 14.27 appears as one if the parameter is set to 0.0.) By
default, Pr 14.09 is set to 10.01 (drive OK) so that the PID controller is
disabled if the drive is tripped. When the PID controller is disabled the
output is zero and all the internal state variables (i.e. integrator
accumulator etc.) are held at zero.
If Pr 14.18 is zero, the upper limit (Pr 14.13 ) defines the maximum
positive output for the PID controller and the lower limit defines the
minimum positive or maximum negative output. If symmetrical limits are
selected, i.e. Pr
14.18 =c1, then the upper limit defines the maximum
positive or negative magnitude for the PID output. When any of the limits
is active then the integrator accumulator is held.
When this parameter is set to OFF (0) the integrator operates normally.
Setting this parameter to On (1) will cause the integrator value to be
held. Setting this parameter does not prevent the integrator from being
reset to zero if the PID controller is disabled.
14.07 PID 1 reference slew-rate limit
14.37 PID 2 reference slew-rate limit
RW Uni US
Ú
0.0 to 3200.0 s
Ö
0.0
14.08 PID 1 enable
RW Bit US
Ú
OFF (0) or On (1)
Ö
OFF (0)
14.09 PID 1 optional enable source parameter 1
RW Uni PT US
Ú
Pr 0.00 to Pr 50.99
Ö
Pr 0.00
14.10 PID 1 proportional gain
14.40 PID 2 proportional gain
RW Uni US
Ú
0.000 to 4.000
Ö
1.000
14.11 PID 1 integral gain
14.41 PID 2 integral gain
RW Uni US
Ú
0.000 to 4.000
Ö
1.000
14.12 PID 1 differential gain
14.42 PID 2 differential gain
RW Uni US
Ú
0.000 to 4.000
Ö
1.000
14.13 PID 1 output upper limit
14.43 PID 2 output upper limit
RW Uni US
Ú
0.00 to 100.00 %
Ö
100.00
14.14 PID 1 output lower limit
14.44 PID 2 output lower limit
RW Uni US
Ú
±
100.00 %
Ö
-100.00
14.15 PID 1 output scaling
14.45 PID 2 output scaling
RW Uni US
Ú
0.000 to 4.000
Ö
1.000
14.16 PID 1 output destination parameter
14.46 PID 2 output destination parameter
RW Uni DE PT US
Ú
Pr 0.00 to Pr 50.99
Ö
Pr 0.00
14.17 PID 1 integrator hold
14.47 PID 2 integrator hold
RW Bit NC US
Ú
OFF (0) or On (1)
Ö
OFF (0)
14.18 PID 1 symmetrical limit enable
14.48 PID 2 symmetrical limit enable
RW Bit US
Ú
OFF (0) or On (1)
Ö
OFF (0)
14.19 PID 1 main reference
14.49 PID 2 main reference
RO Bi NC PT US
Ú
±
100.00 %
Ö
14.20 PID 1 reference
14.50 PID 2 reference
RO Bi NC PT US
Ú
±
100.00 %
Ö
14.21 PID 1 feedback
14.51 PID 2 feedback
RO Bi NC PT US
Ú
±
100.00 %
Ö
14.22 PID 1 error
14.52 PID 2 error
RO Bi NC PT US
Ú
±
100.00 %
Ö
14.23 PID 1 reference scaling
14.53 PID 2 reference scaling
RW Uni US
Ú
0.000 to 4.000
Ö
1.000