ADC10_A Registers
726
SLAU208Q – June 2008 – Revised March 2018
Copyright © 2008–2018, Texas Instruments Incorporated
ADC10_A
27.3.9 ADC10LO Register
ADC10_A Window Comparator Low Threshold Register
Figure 27-20. ADC10LO Register
15
14
13
12
11
10
9
8
Reserved
Low_Threshold
r0
r0
r0
r0
r0
r0
rw-(0)
rw-(0)
7
6
5
4
3
2
1
0
Low_Threshold
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
Table 27-11. ADC10LO Register Description
Bit
Field
Type
Reset
Description
15-10
Reserved
R
0h
Reserved. Always reads as 0.
9-0
Low_Threshold
RW
0h
The 10-bit threshold value needs to be right justified. Bit 9 is the MSB. Bits 15-10
are 0 in 10-bit mode, and bits 15-8 are 0 in 8-bit mode. This data format is used
if ADC10DF = 0.
27.3.10 ADC10LO Register, Twos-Complement Format
ADC10_A Window Comparator Low Threshold Register, Twos-Complement Format
Figure 27-21. ADC10LO Register
15
14
13
12
11
10
9
8
Low_Threshold
rw-(1)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
7
6
5
4
3
2
1
0
Low_Threshold
Reserved
rw-(0)
rw-(0)
r0
r0
r0
r0
r0
r0
Table 27-12. ADC10LO Register Description
Bit
Field
Type
Reset
Description
15-6
Low_Threshold
RW
200h
The 10-bit threshold value needs to be left justified if twos-complement format is
chosen. Bit 15 is the MSB. Bits 5-0 are 0 in 10-bit mode, and bits 7-0 are 0 in 8-
bit mode. This data format is used if ADC10DF = 1.
5-0
Reserved
R
0h
Reserved. Always reads as 0.